On-chip peripherals
ST7LUS5, ST7LU05, ST7LU09
Table 51. ADC clock speed configuration
fADC
fCPU/2
fCPU
fCPU/4
ADCDRL SLOW bit
0
0
1
ADCCSR SPEED bit
0
1
x
Table 52. ADC register map and reset values
Address Register
(Hex.)
label
7
6
5
4
3
2
1
0
0034h
t(s) 0035h
OObbssoolleettee PPrroodduucctt((ss)) -- OObbssoolleettee PPrroodduucct(s) 0036h
ADCCSR
Reset value
ADCDRH
Reset value
ADCDRL
Reset value
EOC SPEED ADON
0
0
0
0
CH2 CH1 CH0
0
0
0
0
D9
D8
D7
D6
D5
D4
D3
D2
0
0
0
0
0
0
0
0
SLOW
D1
D0
0
0
0
0
0
0
0
0
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