ST7FLU05MCE View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST7FLU05MCE

8-bit low cost, low pin-count MCU for automotive, with single voltage Flash memory, ADC, timers

STMicroelectronics 

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ST7LUS5, ST7LU05, ST7LU09

Instruction set

Table 59. Instruction groups (continued)

Group

Instructions

Compare and tests

CP TNZ BCP

Logical operations

AND OR XOR CPL NEG

Bit operation

Conditional bit test and branch

BSET BRES

BTJT BTJF

Arithmetic operations

ADC ADD SUB SBC MUL

Shift and rotates

SLL SRL SRA RLC RRC SWAP SLA

Unconditional jump or call

JRA JRT JRF JP CALL CALLR NOP RET

OObbssoolleettee PPrroodduucctt((ss)) -- OObbssoolleettee PPrroodduucctt((ss)) 11.2.1

Conditional branch

Interruption management

Condition code flag modification

JRxx

TRAP WFI

SIM RIM

HALT IRET

SCF RCF

Using a prebyte

The instructions are described with 1 to 4 bytes.

In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three

different prebyte opcodes are defined. These prebytes modify the meaning of the instruction

they precede.

The whole instruction becomes:

PC-2 End of previous instruction

PC-1 Prebyte

PC Opcode

PC+1 Additional word (0 to 2) according to the number of bytes required to compute

the effective address

These prebytes enable instruction in Y as well as indirect addressing modes to be

implemented. They precede the opcode of the instruction in X or the instruction using direct

addressing mode. The prebytes are:

PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent

addressing mode by a Y one.

PIX 92

Replace an instruction using direct, direct bit or direct relative addressing

mode to an instruction using the corresponding indirect addressing mode.

It also changes an instruction using X indexed addressing mode to an

instruction using indirect X indexed addressing mode.

PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.

Illegal opcode reset

In order to provide enhanced robustness to the device against unexpected behavior, a

system of illegal opcode detection is implemented. If a code to be executed does not

correspond to any opcode or prebyte value, a reset is generated. This, combined with the

Watchdog, allows the detection and recovery from an unexpected fault or interference.

Note:

A valid prebyte associated with a valid opcode forming an unauthorized combination does

not generate a reset.

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