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ST7LITE20F2 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
'ST7LITE20F2' PDF : 170 Pages View PDF
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
On-chip peripherals
11.1.6
Register description
Control register (CR)
Read / Write
Reset value: 0111 1111 (7Fh)
7
0
WDGA
T6
T5
T4
T3
T2
T1
T0
Note:
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by hardware after a reset.
When WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
This bit is not used if the hardware watchdog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset is produced when it rolls over from
40h to 3Fh (T6 becomes cleared).
Table 32. Watchdog timer register map and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
002Eh
WDGCR
Reset value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
11.2
11.2.1
12-bit autoreload timer 2 (AT2)
Introduction
The 12-bit Autoreload Timer can be used for general-purpose timing functions. It is based
on a free-running 12-bit upcounter with an input capture register and four PWM output
channels. There are 6 external pins:
– Four PWM outputs
– ATIC pin for the Input Capture function
– BREAK pin for forcing a break condition on the PWM outputs.
Doc ID 8349 Rev 5
73/166
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