ST7LITE20F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE20F2
STMicroelectronics
'ST7LITE20F2' PDF : 170 Pages View PDF
On-chip peripherals
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
to mask the interrupt generated when the CMPF bit is set.
0: CMPF interrupt disabled.
1: CMPF interrupt enabled.
Counter register high (CNTRH)
Read only
Reset value: 0000 0000 (000h)
15
8
0
0
0
0
CNTR11 CNTR10 CNTR9 CNTR8
Counter register low (CNTRL)
Read only
Reset value: 0000 0000 (000h)
7
CNTR7
CNTR6
CNTR5
CNTR4
CNTR3
CNTR2
CNTR1
0
CNTR0
● Bits 15:12 = Reserved
● Bits 11:0 = CNTR[11:0] Counter value
This 12-bit register is read by software and cleared by hardware after a reset. The
counter is incremented continuously as soon as a counter clock is selected. To obtain
the 12-bit value, software should read the counter value in two consecutive read
operations, LSB first. When a counter overflow occurs, the counter restarts from the
value specified in the ATR register.
Autoreload register (ATRH)
Read / Write
Reset Value: 0000 0000 (00h)
15
8
0
0
0
0
ATR11
ATR10
ATR9
ATR8
● Bits 15:12 = Reserved
● Bits 11:0 = ATR[11:0] Counter value
This 12-bit register is read by software and cleared by hardware after a reset. The
counter is incremented continuously as soon as a counter clock is selected. To obtain
the 12-bit value, software should read the counter value in two consecutive read
operations, LSB first. When a counter overflow occurs, the counter restarts from the
value specified in the ATR register.
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Doc ID 8349 Rev 5
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