ST7LITE20F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE20F2
STMicroelectronics
'ST7LITE20F2' PDF : 170 Pages View PDF
On-chip peripherals
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
11.2.2
Main features
● 12-bit upcounter with 12-bit autoreload register (ATR)
● Maskable overflow interrupt
● Generation of four independent PWMx signals
● Frequency 2 kHz-4 MHz (@ 8 MHz fCPU)
– programmable duty-cycles
– polarity control
– programmable output modes
– maskable Compare interrupt
● Input capture
– 12-bit input capture register (ATICR)
– triggered by rising and falling edges
– maskable IC interrupt.
Figure 34. Block diagram
ATIC
12-bit input capture register
ATICR
IC interrupt
ATCSR
request
OVF interrupt
request
0 ICF ICIE CK1 CK0 OVF OVFIE CMPIE
fLTIMER
(1 ms
timebase
@ 8MHz)
fCPU
32 MHz
fCOUNTER
CNTR
CMPF0
CMPF1
CMPF2
CMPF3
12-bit upcounter
12-bit autoreload register
ATR
CMP
interrupt
request
DCR0H
Preload
DCR0L
Preload
on OVF Event
if TRAN=1
12-bit duty cycle value (shadow)
4 PWM channels
CMPFx bit
Comp-
pare
OEx bit
OPx bit
fPWM polarity
PWMx
11.2.3
Functional description
PWM mode
This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx
output pins. The PWMx output signals can be enabled or disabled using the OEx bits in the
PWMCR register.
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Doc ID 8349 Rev 5
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