STA310
Address: 0xAE
Type: R/WS??
Software Reset: NC
Hardware Reset: 0
Description:
Bitfield
Description
3D_VCR
This bit selects "3-D sound" on the VCR
channels using SRS processing
(depending on the PDEC registers and ):
0: Standard sound (disable "3-D sound"),
1: Enable "3-D sound".
COPY
This bit is used to copy "Left/Right"
channels to "VCR" channels:
0: no copy,
1: copy enable.
PRL
This bit enables a "ProLogic downmix" on
the "VCR" channels:
0: Disable,
1: Enable.
STEREO
This bit enables a "2/0 downmix" on the
"VCR" channels:
0: Disable,
1: Enable.
Note:
1. To have both "3-D sound" on the "VCR" and "Left/Right"
channels, the setup is:
VCR_MIX = 0x02 and PDEC = 0x40 for SRS process-
ing,
VCR_LDLY
VCR left channel delay
7654321
0
LEFT_VCR_DELAY
Address: 0xAF
Type: R/WS??
Software Reset: NC
Hardware Reset: 0
Description:
This register contains the VCR left channel delay val-
ue. See note after next register description.
VCR_RDLY
VCR right channel delay
7
6
5
4
3
2
1
0
RIGHT_VCR_DELAY
Address: 0xAF
Type: R/WS??
Software Reset: NC
Hardware Reset: 0
Description:
This register contains the VCR right channel delay
value. The values for LEFT_VCR_DELAY and
RIGHT_VCR_DELAY are taken into account only
when register.bit .DLY = ’1’.
9.27 Miscellaneous
BREAKPOINT
To be defined
7
6
5
4
3
2
1
0
Reserved
Address + 0x2B
Type: R/W
Software Reset: NC
Hardware Reset: 0
Description:
This register must be set to 0x08.
CLOCKCMD
To be defined
7
6
5
4
3
2
1
0
Reserved
Address: 0x3A
Type: R/W
Software Reset: NC
Hardware Reset: 0
Description:
This register must be set to 0x00.
86/90