STA310 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA310' PDF : 90 Pages View PDF
STA310
A.2 Description of the architecture
The MMDSP+ DSP core can access 5 banks of RAM/ROM memories:
- the 32K instruction ROM,
- the 768 words instruction development RAM,
- X_memory 19K x 24 RAM,
- Y_memory 18 K x 24 ROM,
- Y_memory 1K x 24 RAM.
The DSP core can also access some dedicated and general purpose peripherals. These peripherals (called
MMIO peripherals) are mapped as memory locations of the X memory space of the MMDSP+ DSP core. On top
of the front-end dedicated ones, the list of the peripherals is the following:
- Four PCM out I2S/Sony (16,18,20,24 bits) serial output interfaces are provided to connect, typically,
to external DACs. This interface and the Audio PLL provide the Oversampling clocks and the serial
clocks necessary to interface the DACs .This interface provides up to 8 independent audio channels.
A “DMA PCM” MMIO block makes the link between the X data memory of the DSP core (which can
store the audio samples) and the I2S/Sony serial interfaces. This MMIO block is a DMA (Direct Mem-
ory Access) and handles automatically the transfer of data by blocks. This peripheral implements also
an hardware mechanism to support delayed channels. Each channel can de delayed (resolution 1
sample) by a programmable number of data samples. This function is totally transparent to the user.
- A 256 x 8 address space is shared between the MMDSP+ core (as MMIO peripheral) and the external
world of the STA310 through the I2C Slave interface or the Host parallel interface. This area is divided
mainly in 2 parts:
a 192 x 8 general purpose RAM area,
a 64 x (1 to 8 bits) area of specific registers.
- The two PLLs (Audio PLL and System PLL) can be controlled by the DSP itself (thru the MMIO bus)
or by the external world of the STA310 (thru the I2C Slave I/F or the Host parallel I/F).
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