Register description
STA333BW
Table 8. Register summary (continued)
Addr Name
D7
D6
D5
0x1F
0x20
0x21
A1CF3
A2CF1
A2CF2
0x22 A2CF3
0x23
0x24
0x25
0x26
0x27
B0CF1
B0CF2
B0CF3
CFUD
MPCC1
Reserved
0x28 MPCC2
0x29
0x2A
0x2B
0x2C
0x2D
DCC1
DCC2
FDRC1
FDRC2
STATUS
PLLUL
FAULT
UVFAULT
D4
D3
C3B[7:0]
C4B[23:16]
C4B[15:8]
C4B[7:0]
C5B[23:16]
C5B[15:8]
C5B[7:0]
RA
MPCC[15:8]
MPCC[7:0]
DCC[15:8]
DCC[7:0]
FDRC[15:8]
FDRC[7:0]
Reserved OCFAULT
D2
R1
OCWARN
D1
WA
TFAULT
D0
W1
TWARN
6.1
6.1.1
Configuration registers (addr 0x00 to 0x05)
Configuration register A (addr 0x00)
D7
D6
D5
D4
FDRB
TWAB
TWRB
IR1
0
1
1
0
Master clock select
Table 9. Master clock select
Bit
R/W
RST
Name
0
R/W
1
MCS0
1
R/W
1
2
R/W
0
MCS1
MCS2
D3
D2
D1
D0
IR0
MCS2
MCS1
MCS0
0
0
1
1
Description
Selects the ratio between the input I2S sample
frequency and the input clock.
The STA333BW supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
z 32.768 MHz for 32 kHz
z 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
z 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
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Doc ID 13773 Rev 3