STA333BW View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STA333BW
STMicroelectronics
'STA333BW' PDF : 67 Pages View PDF
Register description
STA333BW
Thermal warning recovery bypass
Table 13. Thermal warning recovery bypass
Bit R/W RST
Name
Description
5
R/W
1
TWRB
0: thermal warning recovery enabled
1: thermal warning recovery disabled
This bit sets the behavior of the IC after a thermal warning disappears. If TWRB is enabled
the device automatically restores the normal gain and output limiting is no longer active. If it
is disabled the device keeps the output limit active until a reset is asserted or until TWRB set
to 0. This bit works in conjunction with TWAB
Thermal warning adjustment bypass
Table 14. Thermal warning adjustment bypass
Bit R/W RST
Name
Description
6
R/W
1
TWAB
0: thermal warning adjustment enabled
1: thermal warning adjustment disabled
Bit TWAB enables automatic output limiting when a power stage thermal warning condition
persists for longer than 400ms. When the feature is active (TWAB = 0) the desired output
limiting, set through bit TWOCL (-3 dB by default) at address 0x37 in the RAM coefficients
bank, is applied. The way the limiting acts after the warning condition disappears is
controlled by bit TWRB.
Fault detect recovery bypass
Table 15. Fault detect recovery bypass
Bit R/W RST
Name
Description
7
R/W
0
FDRB
0: fault detect recovery enabled
1: fault detect recovery disabled
6.1.2
The on-chip power block provides feedback to the digital controller which is used to indicate
a fault condition (either overcurrent or thermal). When fault is asserted, the power control
block attempts a recovery from the fault by asserting the 3-state output, holding it for period
of time in the range of 0.1 ms to 1 second, as defined by the fault-detect recovery constant
register (FDRC registers 0x2B-0x2C), then toggling it back to normal condition. This
sequence is repeated as log as the fault indication exists. This feature is enabled by default
but can be bypassed by setting the FDRB control bit to 1. The fault condition is also
asserted by a low-state pulse of the normally high INT_LINE output pin.
Configuration register B (addr 0x01)
D7
C2IM
1
D6
C1IM
0
D5
DSCKE
0
D4
SAIFB
0
D3
SAI3
0
D2
SAI2
0
D1
SAI1
0
D0
SAI0
0
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Doc ID 13773 Rev 3
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