STE100A View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

STE100A

PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STMicroelectronics 

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General EEPROM format description

5

General EEPROM format description

STE10/100A

Table 15. Connection type definition

Offset Length

Description

0

2

STE10/100A signature: 0x81, 0x09

Format major version: 0x02,

2

1

old ROM format version 0x01 is for STE10/100A-MAC only.

3

1

Format minor version: 0x00

4

4

Reserved

8

6

IEEE network address: ID1, ID2, ID3, ID4, ID5, ID6

IEEE ID checksum1:

E

1

Sm0=0, carry=0

SUM=Sm6 where Smi=(Smi-1<<1)+(carry from shift)+IDi

IEEE ID checksum2:

F

1

Reserved, should be zero.

10

1

PHY type, 0xFF: Internal PHY (STE10/100A only)

11

1

Reserved, should be zero

12

2

Default connection type, see Table 15

14

0B Reserved, should be zero

Flow control field,

1F

1

00: Disable flow control function,

01: Enable flow control function.

20

2

PCI device ID

22

2

PCI vendor ID

24

2

PCI subsystem ID

26

2

PCI subsystem vendor ID

28

1

MIN_GNT value

29

1

MAX_LAT value

2A

4

Cardbus CIS pointer

2E

2

CSR18 (CR) bit 31-16 recall data

30

4E Reserved, should be zero

7E

2

CheckSum, the least significant two bytes of FCS for data stored in offset

0..7D of EEPROM

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