STI5512 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STI5512' PDF : 23 Pages View PDF
CONFIDENTIAL ®
STi5512
SET TOP BOX BACKEND DECODER
WITH INTEGRATED HOST PROCESSOR
PRODUCT PREVIEW
s High performance graphics system
• High resolution chroma mode (4:4:4) for RGB output
• 2 to 8 bits per pixel OSD options
• Link list control
• 4-bit mixing factor by region or 6-bit mixing for each
CLUT entry (anti-aliasing)
• 8-bit Y, U and V resolution palette
• Extra YUV plane for background images or graphics
• 2D, paced BLT engine with “fill” function
• Anti-flicker and anti-flutter filters
s Enhanced 32-bit VL-RISC CPU - 60 MHz clock
• Fast integer/bit operation and very high code density
s High performance memory/cache subsystem
• 2 Kbytes instruction cache, 2 Kbytes data cache or
SRAM, 4 Kbytes SRAM
• 200 Mbytes/s maximum bandwidth
s Combined video and audio decoder core
• Video decoder fully supports MPEG-2 MP@ML.
Letter box (16:9 and 14:9), 2:1, 3:1, 4:1 downsizing
• Memory reduction - PAL MP@ML in 12 Mbits
• Audio decoder supports layers 1 and 2 of MPEG 1,
and an AC-3 interface to an external decoder
• Digital YCrCb output in 4:2:2 format
s PAL/NTSC/SECAM encoder
• Outputs RGB with 10-bit DACs and CVBS, Y, C and
component output (YUV) with 10-bit DACS
• Separate OSD control for RGB and CVBS outputs
• Genlock support
s High performance SDRAM memory interface
• Supports two 16- or one 64-Mbit 100 MHz SDRAMs
• Accessible by MPEG decoder, PTI, DMAs and CPU
• High bandwidth access from CPU allows high
performance OSD operations
s Programmable external memory interface (EMI)
• Support for SDRAM included
s Programmable transport interface
• Parallel or serial input
• Supports DVB bit-streams
• More than 32 PIDs supported
• DVB descrambler
• 32 SI/PSI filters of 8 bytes
s Vectored interrupts - 8 prioritized levels
s Interfaces and DMA engines
• 2 SmartCard interfaces, 2 UARTs, 2 I2C / SPI
controllers, 3 PWM outputs, 4 timers, 3 capture
timers
• Block move DMA
• Teletext interface, input from external source
• IEEE 1284 port, or IEEE 1394 A/V link layer
interface
s Low power controller/real time clock/watchdog
s JTAG Test Access Port
s Professional toolset support
• ANSI C compiler and libraries
• Advanced debugging tools
s Non-intrusive debug controller
• Hardware breakpoints
• Real time trace
APPLICATIONS
s Set top boxes to DVB standards.
Block move
DMA
ST20
CPU
Programmable
transport
interface
IEEE 1394
link layer
interface
IEEE 1284
interface
Interrupt
controller
1 OS-Link
2 UARTs
2 I2C
3 PWM
Diagnostic
controller
and system
services
2 SmartCard
interfaces
(ASC)
2 Kbytes
instruction
cache
and 2 Kbytes
data cache
4 Kbytes
SSRRAAMM
EMI
MPEG
audio and
external
decoder I/F
MPEG
video
decoder
PAL/NTSC
/SECAM
encoder
Teletext
interface
10 June 1999
7110123 B
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice
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