STLC5046 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC5046' PDF : 27 Pages View PDF
STLC5046
PIN DESCRIPTION (continued)
ANALOG
N.
Name Type
Function
35
VFXI0
AI TX Input Amplifier channel 0. Typ 1MΩ input impedance
38
VFXI1
AI TX Input Amplifier channel 1. Typ 1MΩ input impedance
43
VFXI2
AI TX Input Amplifier channel 2. Typ 1MΩ input impedance
46
VFXI3
AI TX Input Amplifier channel 3. Typ 1MΩ input impedance
40
CAP
AI AGND Voltage filter pin. A 100nF capacitor must be connected between ground and
this pin.
POWER SUPPLY
25, 36, VCC/0/1/2/3/
37, 44,
4/5
45, 56,
26,30, VEE/0/1/2/3/
31, 50,
4/5
51,55
9
VDD
8
VSS
41
SUB
APS
APS
DPS
DPS
DPS
Total 6 pins: 3.3V analog power supplies, should be shorted together, require 100nF
decoupling capacitor to VEE.
Total 6 pins: analog ground, should be shorted together.
Digital Power supply 3.3V, require 100nF decoupling capacitor to VSS.
Digital Ground
Substrate connection. Must be shorted together with VEE and VSS pins as close as
possible the chip.
NOT CONNECTED
15, 16,
17, 18,
32, 34,
47, 49,
64
N.C.
1,2,63
RES
Not Connected.
Reserved: must be left not connected.
DIGITAL
27
M0
DI Mode select, see M1
54
M1
DI
M1
M0 Mode Select
0
1 Pin-strap mode: Basic functions selected by proper pin strapping
1
0 MCU mode: Device controlled via serial interface
0
0 Reset status
1
1 Not Allowed
13
MCLK
DI Master Clock Input.
Four possible frequencies can be used:
1.536/1.544 MHz; 2.048 MHz; 4.096 MHz; 8.192 MHz.
The device automatically detect the frequency applied.
This signal is also used as bit clock and it is used to shift data into and out of the DR
and DX pins.
12
TSX
ODO Transmit Time Slot (open drain output, 3.2mA). Normally it is floating in high
impedance state except when a time slot is active on the DX output. In this case TSX
output pulls low to enable the backplane line driver.
11
DX
DTO Transmit PCM interface. It remains in high impedance state except during the
assigned time slots during wich the PCM data byte is shifted out on the rising edge of
MCLK.
10
DR
DI Receive PCM interface. It remains inactive except during the assigned receive time
slots during which the PCM data byte is shifted in on the falling edge of MCLK.
61
IO7
DIO Slic control I/O pin #7. Can be programmed as input or output via DIR register.
Depending on content of CONF register can be a static input/output or a dynamic
input/output synchronized with the CSn output signals controlling the SLICs.
4/27
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