STLC5046
Figure 3. MCU mode: Time - Slot Assignment
FS
Receive Time Slot
FS
Transmit Time Slot
TS0
DXAn Reg.
D7..................D0
D7..................D0
TS23/31/61/127
DRAn Reg.
when the preamplifier gain is set 0dB or 0.66Vpp
if the gain is set to 3.52dB (MCU mode only);
higher levels must be reduced through proper di-
viders.
Typical impedance of VFXI input is 1Mohm.
RECEIVE PATH
The received PCM signal DR through the de-
coder section, the gain select block and the D/A
converter is converted in an analog signal which
is transfered to VFRO output through an ampli-
fier stage.
In MCU mode a programmable gain block before
the A/D conversion allows to set receive gain in
12dB range, with steps <0.1dB by writing proper
code into GRXn register.
The amplifier gain can be programmed with five
different values by means of RXG Register:
0dB -1.94dB -4.44dB -7.96dB -13.98dB.
Setting GRXn=00h , the receive signal is muted
and VFRO output is set to AGND.
A/µ coding Law is selected by bit5 (AMU) of
CONF reg.
Setting LIN = 1 (bit6 of CONF reg.) the Linear
coding Law is selected (16bits); in this case the
signal received on DR will take two adjacent PCM
time slots.
in pin Strap mode only two values of Receive
Gain can be selected according to the level of
GRn control input (in Pin Strap)
GRn = 1 selects the gain corresponding to GRXn
= E2h, RXG = 0dB (-0.8dB)
GRn = 0 selects the gain corresponding to GRXn
= AFh, RXG = -1.94dB (-4.3dB)
Different gain value is obtained through proper
voltage divider.
A/µ coding Law is selected according to AMU pin
level:
AMU=0 µ-Law selected.
AMU=1 A-Law selected.
VFRO output, referred to AGND must be AC
coupled to the load, referred to VSS, to prevent a
DC current flow.
VFRO has a drive capability of 1.0mA (peak
value), with a max AC swing of 2Vpp.
In order to get the best noise performances it is
recommended to keep the GRX value as close as
possible to the maximum (FFh) setting properly
the additional attenuation by means of RXG.
PCM INTERFACE
The STLC5046 dedicate five pins (six in pin strap
mode) to the interface with the PCM highways.
MCLK represents the bit clock and is also used
by the device as a source for the clock of the in-
ternal Sigma Delta converter timings. Four possi-
ble frequencies can be used: 1.536/1.544MHz
(24 channels PCM frame); 2048MHz (32 chan-
nels PCM frame); 4.096MHz (64 channels PCM
frame); 8.192MHz (128 channels PCM frame).
The operating frequency is automatically de-
tected by the device when both MCLK and FS
are applied. MCLK is synchronizing both the
transmit data (DX) and the receive data (DR).
MCU mode:
The Frame Sync. signal FS is the common time
base for all the four channels; Short (one MCLK
period) or Long (more than one MCLK period)
FS are allowed.
Transmit and Receive programmable Time-Slots
are framed to an internal sync. signal that can be
coincident with FS or delayed of 1 to 7 MCLK cy-
cles depending on the programming of PCMSH
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