TDA7505
Electrical specifications
4.3.4 General interface electrical characteristics
Table 8.
Symbol
General interface electrical characteristics
Parameter
Test condition
Min. Typ. Max. Unit
lil
Low level input current without pull-up
device
Vi = 0V(1)
1
μA
lih
High level input current without pull-up
device
Vi = VDD3V3 (1)
1
μA
Ioz
Tri-state output leakage without pull
up/down device
Vo = 0V or VDD3V3(1)
1
μA
IozFT
5V tolerant tri-state output leakage
without pull up/down device
Vo = 0V or VDD3V3(1)
Vo = 5.5V
1
μA
1
7
μA
Ilatchup I/O latch-up current
Vi < 0V, Vi > VDD3V3
200
mA
Vesd Electrostatic protection
Leakage, 1μA (2)
2000
V
1. The leakage currents are generally very small, <1nA. The value given here, 1 A, is a maximum that can occur after an
electrostatic stress on the pin.
2. Human Body Model.
4.3.5 High voltage CMOS interface DC electrical characteristics
Table 9. High voltage CMOS interface DC electrical characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Vil Low Level Input Voltage
3.0V<VDD3V3<3.6V
0.3*VDD3V3 V
Vih High Level Input Voltage 3.0V<VDD3V3<3.6V
0.5*VDD3V3
V
Vhyst Schmitt trigger hysteresis 3.0V<VDD3V3<3.6V
0.8
Vol Low level output Voltage
Iol = XmA (1),(2)
V
0.1*VDD3V3 V
Voh High level output Voltage
0.89*VDD3V3
V
1. Takes into account 200mV voltage drop in both supply lines.
2. X is the source/sink current under worst-case conditions and is depicted for every I/O or output pin in the pin description.
4.3.6 DSP core
Table 10. DSP core
Symbol
Parameter
Fdsp DSP clock frequency
Tres Reset signal low state duration
Test condition
Min.
Typ.
75
1
Max.
Unit
MHz
µs
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