TDA7505 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA7505' PDF : 38 Pages View PDF
TDA7505
Electrical specifications
Table 12. SAI interface timing - transmitter
Timing
Description
TDSP(1) Internal DSP clock period (typical 1/75MHz)
tsckt Minimum clock cycle
tlrckts LRCKT setup time
tlrckth LRCKT hold time
tdt SCKT active edge to data out valid
tsckth Minimum SCKT high time
tscktl Minimum SCKT low time
1. TDSP = DSP master clock cycle time = 1/Fdsp
Min Typ Max Unit
13.33
ns
6 TDSP
ns
TDSP
ns
TDSP
ns
TDSP
ns
0.35 tsckr
ns
0.35 tsckr
ns
4.6
SAI protocol
Figure 5. SAI protocol
SCKX
XCKP = 0
SCKX
LRCKX
LRCKX
LRCKX
XCKP = 1
XREL = 0
XLRS = 0
XREL = 0
XLRS = 1
XREL = 1
XLRS = 0
SDY0-2
XDIR = 0
SDY0-2
XDIR = 1
LEFT CHANNEL
RIGHT CHANNEL
1 0 15 14 13 6 5 4 3 2 1 0 15 14 13 6 5 4 3 2 1 0 15 14 13
31 30 29
31 30 29
31 30 29
14
30
15
31
0
1
2
9
25
10
26
11
27
12
28
13
29
14
30
15
31
0
1
2
9
25
10
26
11
27
12
28
13
29
14
30
15
31
0
1
2
Notes: 1) X = R for receiver X = T for transmitter
2) Y = I for receiver Y = O for transmitter
4.7
SPDIF receiver
Table 13. SPDIF receiver
Symbol
Parameter
Test condition
fspdif
Input sampling rate
Fdsp = 75 MHz
Input precision with direct interface to DSP
Input precision with interface to ASRC
Min Typ Max Unit
32
96 kHz
24
bit
20
bit
19/38
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