TDA7505 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA7505' PDF : 38 Pages View PDF
Electrical specifications
4.4
SAI interface timing - receiver
Figure 3. SAI interface timing - receiver
SDI0-2
Valid
LRCKR
SCKR
(RCKP=0)
Valid
t lrckrs
tsdis
tsckrl
t lrckrh
tsdih
tsckrh
tsckr
TDA7505
4.5
Table 11. SAI interface timing - receiver
Timing
Description
TDSP(1) Internal DSP clock period (typical 1/75MHz)
tsckr Minimum clock cycle
tlrckrs LRCKR setup time
tlrckrh LRCKR hold time
tsdid SDI setup time
tsdih SDI hold time
tsckrh Minimum SCKR high time
tsckrl Minimum SCKR low time
1. TDSP = DSP master clock cycle time = 1/Fdsp
Min Typ Max Unit
13.33
ns
6 TDSP
ns
TDSP
ns
TDSP
ns
TDSP
ns
TDSP
ns
0.35 tsckr
ns
0.35 tsckr
ns
SAI interface timing - transmitter
Figure 4. SAI interface timing - transmitter
SDO0-2
Valid
LRCKT
SCKT
(TCKP=0)
Valid
t dt
tscktl
t lrckts
t lrckth
tsckth
tsckt
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