TDA9103 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9103' PDF : 27 Pages View PDF
TDA9103
Figure 8 : Principle Diagram
C Lockdet
13
Eini Filter R0 C0
35
12 11 10
Horizontal
Input 17
LOCKDET
INPUT
INTERFACE
High
COMP1
E2
Low
CHARGE
PUMP
PLL
INHIBITION
Horizontal
Adjust
15
PHASE
ADJUST
VCO
3.2V
OSC
The dynamic behaviour of the PLL is fixed by an
external filter which integrates the current of the
charge pump. A ”CRC” filter is generally used.
PLL1 is inhibited by applying a high level on Pin 35
(PLLinhib) which is a TTL compatible input. The inhibi-
tion results from the opening of a switch located be-
tween the charge pump and the filter (see Figure 8).
The VCO uses an external RC network. It delivers
a linear sawtooth obtained by charge and dis-
charge of the capacitor, by a current proportionnal
to the current in the resistor. typical thresholds of
sawtooth are 1.6V and 6.4V.
Figure 9
PLL1F
12
Figure 10 : Details of VCO and Fhmin Adjustment
The control voltage of the VCO is typically com-
prised between 1.6V and 6V. The theoretical fre-
quency range of this VCO is in the ratio 1 → 3.75,
but due to spread and thermal drift of external
components and the circuit itself, the effective fre-
quency range has to be smaller (e.g. 30kHz →
82kHz). Inthe absenceof synchronisationsignal the
control voltage is equal to 1.6V typ. and the VCO
oscillates on its lowest frequency (free frequency).
The synchro frequencyhas to be always higher than
the free frequency and a margin has to be taken. As
an example for a synchro range from 30kHz to
82kHz, the suggested free frequency is 27kHz. To
compensate for the spread of external components
and of the circuit itself, the free frequency may be
adjusted by a DC voltage on Pin 14 (Fmin adjust)
(see Figure10 for details).
The PLL1 ensures the coincidence between the
leading edge of the synchro signal and a phase
reference obtained by comparison between the
sawtooth of the VCO and an internal DC voltage
adjustable between 2.4V and 4V (by Pin 15). So a
±45° phase adjustment is possible.
Loop 12
Fil ter
(1.6V < V12 < 6V)
FHMINADJ
I0
14
2
a I0
(0.8V < a < 1.2V) 4 I0
2
11
R0
6.4V
1.6V
RS
FLIP FLOP
10 6.4V
C0
1.6V
0 0.75T T
12/27
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