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TDA9103 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
TDA9103
ST-Microelectronics
STMicroelectronics ST-Microelectronics
'TDA9103' PDF : 27 Pages View PDF
Figure 11 : Safety Functions Block Diagram
VCC 30
VCC Checking
-
REF 30 +
TDA9103
SMPS Output
Inhibition
XRAY Protection
XRAY 30 S
Q
VCCoff 30
R
H Output
Inhibition
PLL-Unloocked 30
H-duty Cycle 30
1V 30
Inhibition
-
+
Flyback 30 -
0.7V 30 +
Figure 12 : LOCK/UNLOCK Block Diagram
V Output
Inhibition
Blanking
From
Phase
A
NOR1
20kH-Lock CAP
13
B
NOR2
23 SBLK OUT
Comparator
220nF
6.5V
The TDA9103 also includes a LOCK/UNLOCK
identification block which sense in real-time
wheather the PLL is locked on the incomming
horizontal sync signal or not. The resulting informa-
tion is available on safety blanking output (Pin 23)
where it is mixed with others information (see Fig-
ure 11). The block diagram of the LOCK/UNLOCK
function is described in Figure 12.
The NOR1 gate is receiving the phase comparator
output pulses (which also drives the charge pump).
When the PLL is locked, on point A there is a very
small negative pulse (100ns) at each horizontal
cycle, so after R-C filter, there is a high level on Pin
13 which force SBLK to high level (provided other
inputs on NOR2 are also at low level).
When the PLL is unlocked, the 100ns negative
pulse on A becomesmuch larger and consequently
the average level on Pin 13 will decrease. When it
reaches 6.5V, point B goes to high level forcing
NOR2 open collector output to ”0”.
The status of Pin 13 is approximately the following :
- Near 0V when there is no H-SYNC,
- Between 0 and 4V with H-SYNC frequency differ-
ent from VCO,
- Between 4 and 8V when H-SYNC frequency
= VCO frequency but not in phase,
- Near to 8V when PLL is locked.
It is important to notice that Pin 13 is not an output
pin and must only be used for filtering purpose (see
Figure 12).
Figure 13 : PLL1 Timing Diagram
H Osc
Sawtooth 0.75T
0.25T
Phase REF1
6.4V
2.4V<Vb<4V
Vb
1.6V
H Synchro
Phase REF1 is obtained by comparison between the sawtooth
and a DC voltage adjustable between 2.4V and 4V. The PLL1
ensures the exact coincidence between the signals phase REF
and HSYNS. A ± 45° phase adjustment is possible.
13/27
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