TDA9103 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9103' PDF : 27 Pages View PDF
TDA9103
PLL2
Figure 14 : Dual PLL Block Diagram
C Lockdet
13
Eini Filter R0 C0
35
12 11 10
Horizontal
Input
17
LOCKDET
INPUT
INTERFACE
High
COMP1
E2
Low
CHARGE
PUMP
PLL
INHIBITION
Horizontal
Adjust
15
VCO
OSC
Adjust
Rapcyc
2
RAP
CYC
Cap
PH12
1
High
CHARGE
PUMP
Low
VA
VB
PHASE
3.2V
ADJUST
E2
COMP2 GENPULSE
E1
HFREQ
FAJUST
14
Freq
Adjust
FLYBACK 3 Flyback
PWM
LOGI
PWM
The PLL2 ensures the coincidence between the
leading edge of the shaped flyback signal and a
phase reference signal obtained by comparison of
the sawtooth of the VCO and a constant DC voltage
(3.2V) (see Figure 15).
Figure 15 : PLL2 Timing Diagram
H Osc
Sawtooth 0.75T
0.25T
6.4V
3.2V
1.6V
Flyback
Shapped
Flyback
Phase REF2
H Drive
Ts
Duty Cycle
Phase REF2 is obtained by comparison between the sawtooth and
a 3.2V (constant). The PLL2 ensures the exact coincidence
between the signals phase REF2 and the flyback signal. The duty
cycle of H-drive is adjustable between 30% and 50%.
The phase comparator of PLL2 is similar to the one
of PLL1, it is followed by a charge pump with a
21 SortCOLL
BUFFER
20 SortEM
±0.5mA (typ.) output current.
The flyback input is composed of an NPN transistor.
This input has to be current driven. The maximum
recommanded input current is 2mA (see Fig-
ure 16).
Figure 16 : Flyback Input Electrical Diagram
HFLY 3
400Ω
Q1
20kΩ
GND 0V
Output Section
The H-drive signal is transmitted to the output
through a shaping block ensuring a duty cycle
adjustable from 30% to 50%. In order to ensure a
reliable operation of the scanning power part, the
output is inhibited in the following circumstances :
- VCC too low.
- Xray protection activated.
- During the flyback.
- Output voluntarily inhibited.
The output stage is composed of a Darlington NPN
bipolar transistor. Both the collector and the emitter
are accessible.
14/27
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