TDA9112A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9112A' PDF : 60 Pages View PDF
TDA9112A
8 I²C-BUS CONTROL REGISTER MAP
The device slave address is 8C in write mode and 8D in read mode. The control register map is given in
Table .
Bold weight denotes default value at Power-On-Reset.
I²C-bus data in the adjustment register is buffered and internally applied with discharge of the vertical os-
cillator (65).
In order to ensure compatibility with future devices, all “Reserved” bits should be set to 0.
Table 8. I²C-bus control registers
Sad
D7
D6
D5
D4
D3
D2
D1
D0
WRITE MODE (SLAVE ADDRESS = 8C)
HDutySyncV
HDUTY Horizontal duty cycle
00 1: Synchro.
0: Asynchro.
0
0
0
0
0
0
0
01
1
HPOS Horizontal position
0
0
0
0
0
0
0
HMoiréMode
HMOIRE Horizontal moiré amplitude
02 1: Separated
0: Combined
0
0
0
0
0
0
0
03
B+SyncV
0: Asynchro.
1
0
BREF B+reference
0
0
0
0
0
04
HDyCorTr
0: Not active
1
HVDC-HAMP HVDyCor horizontal amplitude
0
0
0
0
0
0
HDyCorPh
HVDC-HPH HVDyCor horizontal phase
05 1: Middle
0: Start
1
0
0
0
0
0
0
06
BOutPol
0: Type N
1
HVDC-VAMP HVDyCor vertical amplitude
0
0
0
0
0
0
BOutPh
VSIZE Vertical size
07 0: H-flyback
1: H-drive
1
0
0
0
0
0
0
08
EWTrHFr
0: No tracking
1
0
VPOS Vertical position
0
0
0
0
0
SCOR S-correction
09 Reserved
1
0
0
0
0
0
0
CCOR C-correction
0A Reserved
1
0
0
0
0
0
0
VMOIRE Vertical moiré amplitude
0B Reserved
0
0
0
0
0
0
0
PCC Pin cushion correction
0C Reserved
1
0
0
0
0
0
0
KEYST Keystone correction
0D Reserved
1
0
0
0
0
0
0
TCC Top corner correction
0E Reserved
1
0
0
0
0
0
0
BCC Bottom corner correction
0F Reserved
1
0
0
0
0
0
0
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