TDA9112A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9112A' PDF : 60 Pages View PDF
DESCRIPTION OF I²C-BUS SWITCHES AND FLAGS
TDA9112A
Write-to bits
Sad00h/D7 - HDutySyncV
Synchronization of internal application of Hori-
zontal Duty cycle data, buffered in I²C-bus latch,
with internal discharge of Vertical oscillator.
0: Asynchronous mode, new data applied
with ACK bit of I²C-bus transfer on this sub
address
1: Synchronous mode
Sad02h/D7 - HMoiréMode
Horizontal Moiré characteristics.
0: Adapted to an architecture with EHT gener-
ated in deflection section
1: Adapted to an architecture with separated
deflection and EHT sections
Sad03h/D7 - B+SyncV
Same as HDutySyncV, applicable for B+ refer-
ence data
Sad04h/D7 - HDyCorTr
Tracking of Horizontal Dynamic Correction
waveform amplitude with HSIZE adjustment.
0: Not active
1: Active
Sad05h/D7 - HDyCorPh
Phase of start of Horizontal Dynamic Correc-
tion waveform in relation to horizontal fly-
back pulse.
0: Start of the flyback
1: Middle of the flyback
Sad06h/D7 - BOutPol
Polarity of B+ drive signal on BOut pin.
0: adapted to N type of power MOS - high
level to make it conductive
1: adapted to P type of power MOS - low level
to make it conductive
Sad07h/D7 - BOutPh
Phase of start of B+ drive signal on BOut pin
0: End of horizontal flyback or horizontal fre-
quency divided by 2, see BOHEdge bit.
1: With one of edges of line drive signal on
HOut pin, selected by BOHEdge bit
Sad08h/D7 - EWTrHFr
Tracking of all corrections contained in wave-
form on pin EWOut with Horizontal Frequency
0: Not active
1: Active
Sad15h/D7 - VDyCorPol
Polarity of Vertical Dynamic Correction wave-
form (parabola)
0: Concave (minimum in the middle of the pa-
rabola)
1: Convex (maximum in the middle of the pa-
rabola)
Sad16h/D0 - HLockEn
Enable of output of Horizontal PLL1 Lock/unlock
status signal on pin HLckVBk
0: Disabled, vertical blanking only on the pin
HLckVBk
1: Enabled
Sad16h/D1 - PLL1InhEn
Enable of Inhibition of horizontal PLL1 during
extracted vertical synchronization pulse
0: Disabled, PLL1 is never inhibited
1: Enabled
Sad16h/D2 and D3- PLL1Pump
Horizontal PLL1 charge Pump current
D3 D2
Time Constant
0
0 Slowest PLL1, lowest current
1
0 Moderate Slow PLL1, low current
0
1 Moderate Fast PLL1, high current
1
1 Fastest PLL1, highest current
Sad16h/D4 - SDetReset
Reset to 0 of Synchronization Detection flags
VDet, HVDet and VExtrDet of status register ef-
fected with ACK bit of I²C-bus data transfer into
register containing the SDetReset bit. Also see
description of the flags.
0: No effect
1: Reset with automatic return of the bit to 0
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