TDA9112A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9112A' PDF : 60 Pages View PDF
9.3 Horizontal section
9.3.1 General
The horizontal section consists of two PLLs with
various adjustments and corrections, working on
horizontal deflection frequency, then phase shift-
ing and output driving circuitry providing H-drive
signal on HOut pin. Input signal to the horizontal
section is output of the polarity inverter on H/HVSyn
input. The device ensures automatically that this
polarity be always positive.
9.3.2 PLL1
The PLL1 block diagram is in Figure 5. It consists of
a voltage-controlled oscillator (VCO), a shaper
with adjustable threshold, a charge pump with inhi-
bition circuit, a frequency and phase comparator
and timing circuitry. The goal of the PLL1 is to
make the VCO ramp signal match in frequency the
sync. signal and to lock this ramp in phase to the
sync. signal. On the screen, this offset results in
the change of horizontal position of the picture.
The loop, by tuning the VCO accordingly, gets and
maintains in coincidence the rising edge of input
sync. signal with signal REF1, deriving from the
VCO ramp by a comparator with threshold adjust-
able through HPOS I²C-bus control. The coinci-
dence is identified and flagged by lock detection
circuit on pin HLckVBk as well as by HLock I²C-bus
flag.
The charge pump provides positive and negative
currents charging the external loop filter on HPLL1F
pin. The loop is independent of the trailing edge of
sync. signal and only locks to its leading edge. By
design, the PLL1 does not suffer from any dead
band even while locked. The speed of the PLL1
depends on current value provided by the charge
pump. While not locked, the current is very low, to
slow down the changes of VCO frequency and
thus protect the external power components at
TDA9112A
sync. signal change. In locked state, the currents
are much higher, four different values being se-
lectable via PLL1Pump I²C-bus bits to provide a
means to control the PLL1 speed by S/W. Lower
value make the PLL1 slower, but more stable.
Higher values make it faster and less stable. In
general, the PLL1 speed should be higher for high
deflection frequencies. The response speed and
stability (jitter level) depend on the choice of exter-
nal components making up the loop filter. A “CRCâ€
filter is generally used (see Figure 4).
Figure 4. H-PLL1 filter configuration
HPLL1F
9
R2
C1
C2
The PLL1 is internally inhibited during extracted
vertical sync. pulse (if any) to avoid taking into ac-
count missing or wrong pulses on the phase com-
parator. Inhibition is obtained by forcing the charge
pump output to high impedance state. The inhibi-
tion mechanism can be disabled through
PLL1InhEn I²C-bus bit.
The Figure 7, in its upper part, shows the position of
the VCO ramp signal in relation to input sync.
pulse for three different positions of adjustment of
horizontal position control HPOS.
35/60
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