TDA9112A
Figure 5. Horizontal PLL1 block diagram
H/HVSyn
1
Sync
Polarity
INPUT
INTERFACE
Extracted
V-sync
PLL1
HLckVBk
Blank 3
PLL1InhEn
(I²C) V-sync (extracted)
HLock
(I²C)
HPLL1F RO CO HOscF
9 86 4
LOCK
DETECTOR
High
PLL
INHIBITION
COMP
REF1
CHARGE
PUMP
Low
PLL1Pump
(I²C)
HPosF
10
SHAPER
VCO
HOSC
HPOS
(I²C)
Figure 6. Horizontal oscillator (VCO) schematic diagram
(PLL1 filter)
VHO
HPLL1F 9
+
-
from charge pump
I0
I0
2
4 I0
RO 8
4 HOscF
VHOThrHi +
-
-
VHOThrLo +
RS
Flip-Flop
6 CO
VHOThrHi
VHOThrL
VCO discharge
control
9.3.3 Voltage controlled oscillator
The VCO makes part of both PLL1 and PLL2
loops, being an āoutputā to PLL1 and āinputā to
PLL2. It delivers a linear sawtooth. Figure 6 ex-
plains its principle of operation. The linears are ob-
tained by charging and discharging an external ca-
pacitor on pin CO, with currents proportional to the
current forced through an external resistor on pin
RO, which itself depends on the input tuning volt-
age VHO (filtered charge pump output). The rising
and falling linears are limited by VHOThrLo and
VHOThrHi thresholds filtered through HOscF pin.
At no signal condition, the VHO tuning voltage is
clamped to its minimum (see section 6.4 - page
10), which corresponds to the free-running VCO
frequency fHO(0). Refer to subsection 9.3.1 for for-
mula to calculate this frequency using external
components values. The ratio between the fre-
quency corresponding to maximum VHO and the
one corresponding to minimum VHO (free-running
frequency) is about 4.5. This range can easily be
increased in the application. The PLL1 can only
lock to input frequencies falling inside these two
limits.
36/60