TS68HC901 View Datasheet(PDF) - STMicroelectronics
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MFG CO.
'TS68HC901' PDF : 42 Pages View PDF
TS68HC901
INTERRUPT CONTROL REGISTERS
CMPF interrupt processing is managed by the inter-
rupt enable registers A and B, interrupt pending re-
gisters A and B, and interrupt mask registers A and
B. These registers allow the programmer to enable
or disable individual interrupt channels, mask indi-
vidual interrupt channels, and access pending inter-
rupt status information. In-service registers A and B
allow interrupts to be nested as described hereafter.
The interrupt control registers are shown in fig-
ure 10.
INTERRUPT ENABLE REGISTERS
The interrupt channels are individually enabled or di-
sabled by writing a one or zero, respectively, to the
appropriate bit of interrupt enable register A (IERA)
or interrupt enable register B (IERB). The processor
may read these registers at any time.
When a channel is enabled, interrupts received on
the channel will be recognized by the CMFP and
IRQ will be asserted to the processor, indicating that
interrupt service is required. On the other hand, a di-
sabled channel is completely inactive; interrupts re-
ceived on the channel are ignored by the CMFP.
Writing a zero to a bit of interrupt enable register A
or B will cause the corresponding bit of interrupt pen-
ding register A or B to be cleared. This will terminate
all interrupt service requests for the channel and al-
so negate IRQ, unless interrupts are pending from
other sources. Disabling a channel, however, does
not affect the corresponding bit in interrupt in-ser-
vice registers A or B. So, if the CMFP is in the soft-
ware end-of-interrupt mode and an interrupt is in
service when a channel will remain set until cleared
by software.
INTERRUPT PENDING REGISTERS
When an interrupt is received on an enabled chan-
nel, the corresponding interrupt pending bit is set in
interrupt pending register A or B (IPRA or IPRB). In
a vectored interrupt scheme, this bit will be cleared
when the processor acknowledges the interrupting
channel and the CMFP responds with a vector num-
ber. In a polled interrupt system, the interrupt pen-
ding registers must be read to determine the inter-
rupting channel and then the interrupting pending bit
is cleared by the interrupt handling routine without
performing an interrupt acknowledge sequence.
A single bit of the interrupt pending registers is clea-
red in software by writing ones to all bit positions ex-
cept the bit to be cleared. Note that writing ones to
IPRA and IPRB has no effect on the contents of the
register. A single bit of the interrupt pending regis-
ters is also cleared when the corresponding channel
is disabled by writing a zero to the appropriate bit of
IERA or IERB.
INTERRUPT MASK REGISTERS
Interrupts are masked for a channel by clearing the
appropriate bit in interrupt mask register A or B (IM-
RA or IMRB). Even though an enabled channel is
masked, the channel will recognize subsequent in-
terrupts and set its interrupt pending bit. However,
the channel is prevented from requesting interrupt
service (IRQ to the processor) as long as the mask
bit for that channel is cleared.
If a channel is requesting interrupt service at the time
that its corresponding bit in IMRA or IMRB is clea-
red, the request will cease and IRQ will be negated,
unless another channel is requesting interrupt ser-
vice. Later, when the mask bit is set, any pending in-
terrupt on the channel will be processed according
to the channel’s assigned priority. IMRA and IMRB
may be read at any time.
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