TS68HC901 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TS68HC901' PDF : 42 Pages View PDF
TS68HC901
gle the timer output, and an interrupt may be optio-
nally generated on the timer interrupt channel.
Note that the pulse width measured will include
counts from before the main counter was reloaded.
If the timer data register is written while the pulse is
transitioning to the active state, an indeterminate va-
lue may be written into the main counter.
Once the timer is reprogrammed for another mode,
interrupts will again occur as normally defined by the
edge bit. Note that an interrupt may be generated as
the result of placing the timer into the pulse width
measurement mode or by reprogramming the timer
for another mode. Also, an interrupt may be gene-
rated by changing the state of the edge bit while in
the pulse width measurement mode.
EVENT COUNT MODE OPERATION
In addition to the delay mode and the pulse width
measurement mode, timers A and B may be pro-
grammed to operate in the event count mode. Like
the pulse width measurement mode, the event
count mode also requires an auxiliary input signal,
TAI or TBI, and the interrupt channels normally as-
sociated with I4 and I3 will respond to transitions on
TAI and TBI respectively. General purpose lines I3
and I4 only function as I/O ports.
In the event count mode the prescaler is disabled,
allowing each active transition on TAIand TBI to pro-
duce a count pulse. The count pulse causes the
main counter to decrement by one. When the timer
counts through 01 (hexadecimal), a time out pulse
is generated which will cause the output signal to
toggle and may optionally produce an interrupt via
the associated timer interrupt channel. The timer’s
main counter is also reloaded from the timer data re-
gister. To count transitions reliably, the input signal
may only transition once every four timer clock pe-
riods. For this reason, the input signal must have a
maximum frequency equal to one-fourth that of the
timer clock.
The active edge of the auxiliary input signal is defi-
ned by the associated interrupt channel’s edge bit.
GPIP4 of the AER specifies the active edge for TAI
and GPIP3 defines the active edge for TBI. When
the edge bit is programmed to a one, a count pulse
will be generated on the zero-to-one transition of the
auxiliary input signal. When the edge bit is program-
med to a zero, a count pulse will be generated on
the one-to-zero transition. Also, note that changing
the state of the edge bit while the timer is in the event
count mode may produce a count pulse.
Besides generating a count pulse, the active trans-
ition of the auxiliary input signal will also produce an
interrupt on the I3 or I4 interrupt channel, if the in-
terrupt channel is enabled. Typically, in the event
count mode, these channels are not enabled since
the timer is automatically counting transitions on the
input signal. If the interrupt channel is enabled, the
number of transitions could be counted in the inter-
rupt routine without requiring the use of the timer.
TIMER REGISTERS
The four timers are programmed via three control re-
gisters and four timer data registers. Control regis-
ters TACR and TBCR and timer data registers
TADR and TBDR (refer to figure 5.1) are associated
with timers A and B respectively. Timers C and D are
controlled by the control register TCDCR and the
data registers TCDR and TDDR (refer to Figure 13).
TIMER DATA REGISTERS
Each timer’s main counter is an 8-bit binary down
counter. The value of the main counter may be read
at any time by reading the timer’s data register. The
information read is the value of the counter which
was captured on the last low-to-high transition of the
DS pin.
The main counter is initialized by writing to the ti-
mer’s data register. If the timer is stopped, data is
loaded simultaneously into both the timer data regis-
ter and the main counter. If the timer data register
is written while the timer is enabled, the value is not
loaded into the timer until the timer counts through
01 (hexadecimal). Writing the timer data register
while the timer is counting through 01 (hexadecimal)
will cause an indeterminate value to be loaded into
the timer’s main counter. The four data registers are
shown in Figure 13.
TIMER CONTROL REGISTERS
Bits in the timer control registers select the operation
mode, select the prescaler value, and disable the ti-
mers. Timer control registers TACR and TBCR also
have bits which allow the programmer to reset out-
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