TS68HC901 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TS68HC901' PDF : 42 Pages View PDF
TS68HC901
TIMERS
The CMFP contains four 8-bit timers which provide
many functions typically required in microprocessor
systems. The timers can supply the baud rate clocks
for the on-chip serial I/O channel, generate periodic
interrupts, measure elapsed time, and count signal
transitions. In addition, two timers have waveform
generation capability.
All timers are prescaler/counter timers with a
common independent clock input (XTAL1 or
XTAL2) and are not required to be operated from the
system clock. Each timer’s output signal toggles
when the timer’s main counter times out. Additional-
ly, timers A and B have auxiliary control signals
which are used in two of the operation modes. An
interrupt channel is assigned to each timer and
when the auxiliary control signals are used, a sepa-
rate interrupt channel will respond to transitions on
these inputs.
OPERATION MODES
Timers A and B are full function timers which, in ad-
dition to the delay mode, operate in the pulse width
measurement mode and the event count mode. Ti-
mers C and D are delay timers only. A brief discus-
sion of each of the timer modes follows.
DELAY MODE OPERATION
All timers may operate in the delay mode. In this
mode, the prescaler is always active. The prescaler
specifies the number of timer clock cycles which
must elapse before a count pulse is applied to the
main counter. A count pulse causes the main coun-
ter to decrement by one. When the timer has decre-
mented down to 01 (hexadecimal), the next count
pulse will cause the main counter to be reloaded
from the timer data register and a time out pulse will
be produced. This time out pulse is coupled to the
timer’s interrupt channel and, if the channel is en-
abled, an interrupt will occur. The time out pulse also
causes the timer output pin to toggle. The output will
remain in this new state until the next time out pulse
occurs.
For example, if delay mode with a divide-by-10 pres-
caler is selected and the timer data register is loaded
with 100 (decimal), the main counter will decrement
once every 10 timer clock cycles. After 1,000 timer
clocks, a time out pulse will be produced. This time
out pulse will generate an interrupt if the channel is
enabled (IERA, IERB) and in addition, the timer’s
output line will toggle. The output line will complete
one full period every 2,000 cycles of the timer clock.
If the prescaler value is changed while the timer is
enabled, the first time out pulse will occur at an in-
determinate time no less than one nor more than
200 timer clock cycles. Subsequent time out pulses
will then occur at the correct interval.
If the main counter is loaded with 01 (hexadecimal),
a time out pulse will occur every time the prescaler
presents a count pulse to the main counter. If the
main counter is loaded with 00, a time out pulse will
occur every 256 count pulses.
PULSE WIDTH MEASUREMENT OPERATION
Besides the delay mode, timers A and B may be pro-
grammed to operate in the pulse width measure-
ment mode. In this mode an auxiliary control input
is required ; timers A and B auxiliary input lines are
TAI and TBI. Also, in the pulse width measurement
mode, interrupt channels normally associated with
I4 and I3 will respond to transitions on TAI and TBI,
respectively. General purpose lines I3 and I4 may
still be used for I/O. A conceptual circuit of the timers
17/42
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