VG4616321B View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG4616321B' PDF : 82 Pages View PDF
VIS
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
9 Write and AutoPrecharge command (refer to the following figure)
(RAS = “H” , CAS = “L” , WE = “L” , DSF=”L” , BS = Bank, A9 = ”H”, A0-A7 = Column Address, A8 =
Don’t care)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {burst length + tWR + tRP(min.)}. At full-page burst, only write operation is performed in
this command and the auto precharge function is ignored.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
Bank A
Activate
NOP
CAS latency = 1
tck1,DQ’s
CAS latency = 2
tck2,DQ’s
CAS latency = 3
tck3,DQ’s
NOP
Write A
Auto Precharge
NOP
DIN A0
DIN A1
DIN A0
DIN A1
DIN A0
DIN A1
NOP
tDAL
*
NOP
NOP
tDAL
*
tDAL
*
NOP
tDAL = tWR + tRP
* Begin AutoPrecharge
Bank can be reactivated at completion of tDAL
Burst Write with Auto-Precharge (Burst Length = 2, CAS Latency = 1, 2, 3)
10 Block Write and AutoPrecharge command
(RAS = “H” , CAS = “L” , WE = “H”, DSF = “H” , BS = Bank , A9 = “H” , A3-A7 = Column Address, A8
= Don’t care DQ0-DQ31 = Column Mask)
The Block Write and AutoPrecharge command performs the precharge operation automatically after
the block write operation. Once this command is given, any subsequent command can not occur within a
time delay of {tBPL + tRP (min.)}.
11 Mode Register Set command
(RAS = “L” , CAS = ”L”, WE = “L” , DSF = “L” , BS , A0-A9 = Register Data)
The mode register stores the data for controlling the various operating modes of SGRAM. The Mode
Register Set command programs the values of CAS latency. Addressing Mode and Burst Length in the
Mode register to make SGRAM useful for variety of different applications. The default values of the Mode
Register after power-up are undefined, therefore this command must be issued at the power-up
sequence. The state of pins A0-A9 and BS in the same cycle is the data written in the mode register. One
clock cycle is required to complete the write in the mode register (refer to the following figure ). The mode
register contents can be changed using the same command and the clock cycle requirements during
operation as long as both banks are in the idle state.
Document:1G5-0145
Rev.1
Page 15
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