VIS
CLK
CKE
CS
RAS
T0
T1
tCK2
Preliminary
T2
T3
T4
T5
Clock min
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
T6
T7
T8
T9
T10
CAS
WE
DSF
BS
A9
A0-A8
DQM
DQ Hi-Z
Address key
tRP
PrechargeAll
Mode Register Any
Set Command Command
Mode Register Set Cycle (CAS Latency = 1, 2, 3)
The mode register is divided into various fields depending on functionality.
• Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the
Burst Length to be 1, 2, 4, 8, or full page.
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Burst Length
1
2
4
8
Reserved
Reserved
Reserved
Full Page
Document:1G5-0145
Rev.1
Page 16