VV6801C001 View Datasheet(PDF) - Vision
Part Name
Description
MFG CO.
'VV6801C001' PDF : 23 Pages View PDF
VISION VV6801/5801 PRELIMINARY CUSTOMER DATASHEET Rev 1.1
Control Register Write Timings:
DCK
DIN
CR[19] CR[18]
CR[1] CR[0]
DLAT
DOUT*
20 DCK Cycles
CR[19] CR[18]
CR[1] CR[0]
20 DCK Cycles
Control Register Read Timings:
DCK
DIN
DLAT
y DOUT*
CR[19] CR[18] CR[17]
CR[2] CR[1] CR[0]
r * Only valid when CR[7:5] = 000 (Default)
20 DCK Cycles
ina Figure 6.2 : Serial data transfer protocol
6.3
The Serial Data Word
The 22-bit Serial Data Word (msb first)
lim CR[19]
Reserved VCINE[1] VCINE[0] SWCP D[4] D[3] D[2] D[1]
e CR[8]
Pr SWCP OS[2] OS[1] OS[0] BM[1] BM[0] HCINE CLE
CR[9]
D[0] OCLE RSH
CR[0]
BLE
R/W
Read = 11
Figure 6.3 : Read Data Format
The 22-bit Serial Data Word consists of the two-bit wide R/W flag, and the 20 bits of Control Register data
(CR[0..19].
6.4 Register description
The following tables defines the CR information contained in the messages:
CR
Bit
Function/Comment
0 Bit-line Test Enable
1 Bit-line Clamp Enable
2 Select Horizontal ‘Cine’ mode: Only every second pixel pair is out-
put - i.e. every second pixel from each colour channel.
4,3 Controls the integration mode for black reference lines
7..5 Selects the node that DOUT is monitoring
8 Enables the Sample & Hold circuits on the four output channels
Default
0
1
0
0
0
0
cd24082b.fm
09/09/98: PRELIMINARY
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VISION VV6801/5801 PRELIMINARY CUSTOMER DATASHEET Rev 1.1
CR
Bit
Function/Comment
Default
9 Connects the four black reference output channels together; the
0
default is AVORef cycling through the four channels
10 Enable clamping circuitry on the four output channels
1
15..11 D[4..0] - 5-bit Resistive DAC value; D[4] is msb
16
16 Switch in the Output Stage Sample&Hold Capacitors
0
18..17 Vertical Cine Mode select - subsample vertically
0
19 Reserved
0
6.5 Control Register Definitions
The various bits in the Control Register define operating modes and parameters as follows:
ry 6.5.1 CR[0] - Bit-line Test Enable
Enables testing of the pixel column interconnections. This bit should always be 0.
a 6.5.2 CR[1] - Bit-Line Clamp Enable
in The default is the bit-line clamp enabled, CR[1] = 1, which ensures that if a bit-line goes too low due to a pixel
being heavily over-exposed, the bit-line is clamped to Vbltw-Vtn.
Note: Due to internal variations, the absolute clamp voltage will vary from column to column. Thus, care must
be taken to ensure that the ADC value clips before the bit-line clamp circuits operate otherwise column to
lim column fixed pattern noise will appear in the saturated white regions of the image.
6.5.3 CR[2] - Horizontal Cine Mode
Setting CR[2] = 1 forces the horizontal shift register to read out every second red, green or blue pixel in each
e odd and even field. In this mode 258 pixels instead of 514 pixels are read out per colour per line. (Note: The
buffer columns on the left and right side of the pixel array are always read out, therefore the central 256 pixels
r are valid for each colour channel.)
P CR[8] and CR[16] should also both be low for Horizontal Cine mode.
6.5.4 CR[4:3] - Black Reference Line Integration Mode Select
CR[4] and CR[3] control the selection of the four possible integration modes to the black reference lines. The
Table below defines the code associated with each of the four modes.
CR[4]
0
0
1
1
CR[3]
0
1
0
1
Integration Mode for Black reference
Lines
Permanent Reset.
Minimum Integration (FR)
Same integration time as main array (FI)
Always integrating.
(See Section 2.9 for details of these modes.)
6.5.5 CR[7:5] - Select DOUT output
Output to the DOUT pin is multiplexed under the control of CR[7], CR[6] and CR[5] for test purposes. All three
of these bits must be set to zero for image data to be observed on DOUT.
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