VV6801C001 View Datasheet(PDF) - Vision
Part Name
Description
MFG CO.
'VV6801C001' PDF : 23 Pages View PDF
VISION VV6801/5801 PRELIMINARY CUSTOMER DATASHEET Rev 1.1
all be low.
Event
Timing
Min
Typ
Max
Power On Reset trigger Voltage
PU1
-
2.7
-
RSTB pulse width
PU2-PU1
100
-
-
Settling Time
PU4-PU3
10
-
-
Table 7.2 : Recommended Start-Up Timing.
VDD
SAMRef/
SELRef/
CLAMP
FR/FI/LS
HCLRB/
PU0
4.5V
2.7V
PU1 PU2 PU3
inaryPU4
VCLRB
RSTB
(RSTB should be used to drive HCLRB and VCLRB to reset the sensor)
lim Other References
VRT
Pre VBG
Power-up
First Frame
Units
V
uS
mS
Figure 7.2 : Startup timing sequence
Note: Serial Data can only be sent after RSTB rises.
7.4 Inter-Frame Timing
When a frame is to be taken, the first task is to sample the reference with SAMRef. This signal should be held
high until the first line, which should be for at least 100uS.
If possible, SAMRef should be held high between acquisition of still frames. In order to also ensure that the
AC coupling stages do not drift, SELRef and CLAMP should also be held high.
SAMRef
CLAMP
SELRef
Valid
Pixels
F0
FRAME
F1 F2 F3
F4
Figure 7.3 : Inter Frame Timings
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VISION VV6801/5801 PRELIMINARY CUSTOMER DATASHEET Rev 1.1
Event
Timing
Min
Typ
Max
Units
SAMRef Period
F1-F0
100
-
-
uS
CLAMP overlap of SAMRef[F]
F2-F1
1
uS
SELRef overlap of CLAMP[F}
F3-F2
0.200
uS
Table 7.3 : Inter Frame Timings
7.5 Line Read-Out Timing
The following diagrams and tables define the relative timings of the various control signals required to read
a line of pixels. Not all of the signals shown will be required for all modes of operation, but where they are
y these timing constraints must be observed. Timings for Correlated Double Sampling (using CDSR) are given
r after the standard line read definitions.
LCK is the master clock for the vertical shift registers, for reading and resetting rows. LCK is a latching signal,
a and latches when high (to be reset on the next PCK).
The EVEN signal transitions must precede LCK, and FI & FR must straddle LCK. PXRD must be high when
COLSam is pulsed. EC & EVEN are not latched, and must therefore remain high while reading valid pixels.
in The first line of pixel information is read out when the EVEN and FR signals are both high. If the EVEN signal
is high during the second line period of FR pulse, the line readout sequence will be offset by one line relative
to that outlined in the timing specification. This is due to the FR and FI inputs only being sampled when both
LCK and EVEN are high.
Prelim Note: The recommended timings shown in Table 7.5 to Table 7.9 are preliminary and subject to change.
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