WM8742 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8742' PDF : 65 Pages View PDF
Production Data
WM8742
SAMPLING
RATE
(LRCLK)
128fs
MASTER CLOCK (MCLK) FREQUENCY (MHZ)
192fs
256fs
384fs
512fs
768fs
32kHz
Unavailable Unavailable
8.192
12.288
16.384
24.576
44.1kHz
Unavailable Unavailable 11.2896
16.9344
22.5792
33.8688
48kHz
Unavailable Unavailable
12.288
18.432
24.576
36.864
88.2kHz
11.2896
16.9344
22.5792
33.8688 Unavailable Unavailable
96kHz
12.288
18.432
24.576
36.864 Unavailable Unavailable
176.4kHz
22.5792
33.8688 Unavailable Unavailable Unavailable Unavailable
192kHz
24.576
36.864
Unavailable Unavailable Unavailable Unavailable
Table 11 Typical Relationships Between Master Clock Frequency and Sampling Rate in normal
PCM mode
8FS MODE
Operation in 8FS mode requires that audio data for left and right channels is input separately on two
pins. DINR (pin 4) is the input for right channel data and DINL (pin 2) is the input for left channel
data. Hardware control of the device is not available.
The data can be input in two formats (left or right justified), selectable by register FMT[1:0], and two
word lengths (20 or 24 bit), selectable by register IWL[1:0]. In both modes the data is clocked into the
WM8742 MSB first.
For left justified data the word start is identified by the falling edge of LRCLK. The data is clocked in
on the next 20/24 BCLK rising edges. This format is compatible with industry-standard DSPs and
decoders such as the PMD100.
Figure 19 8FS Mode Left Justified Timing Requirements
For right justified mode, the data is justified to the rising edge of LRCLK and the data is clocked in on
the preceding 20/24 BCLK rising edges before the LRCLK rising edge. This format is compatible with
industry standard DSPs and decoders such as the DF1704 or SM5842.
Figure 20 8FS Mode Right Justified Timing Requirements
w
PD, Rev 4.3, February 2013
25
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