WM8742 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8742' PDF : 65 Pages View PDF
WM8742
In both modes the polarity of LRCLK can be switched using register bit LRP.
Production Data
8FS MODE SAMPLING RATES
Since the data rate in 8FS mode is much faster than in standard PCM mode, there are restrictions on
the MCLK rate that can be used. Specifically, only 512fs and 768fs modes are permitted restricting
the sample rate to a maximum of 8x48kHz. The master clock should be synchronised with LRCLK,
although the WM8742 is tolerant of phase differences or jitter on this clock.
Unlike in normal PCM mode, the master clock detection circuit does not operate in 8FS mode. The
rate must be manually programmed using the control interface.
SAMPLING
RATE
fs
LRCLK
FREQUENCY
(kHz)
8fs
MASTER CLOCK (MCLK)
FREQUENCY (MHz)
512fs
768fs
32kHz
256
16.384
24.576
44.1kHz
352.8
22.5792
33.8688
48kHz
384
24.576
36.864
Table 12 Typical Relationships Between Master Clock Frequency and Sampling Rate in 8FS
Mode
AUDIO INTERFACE DAISY CHAINING
In daisy chain mode the DOUT pin outputs the audio data received on the DIN pin but delayed by two
times the input word length. When this output is connected to the DIN pin of the next device in the
chain, each WM8742 device will simultaneously sample different channel data in the same LRCLK
period. Daisy chaining is only available in DSP audio interface mode and is limited by a maximum
BCLK frequency of 24.576MHz.
REGISTER ADDRESS BIT LABEL DEFAULT
R8
4
DOUT
0
Mode Control 2
08h
Table 13 Daisy Chaining Audio Data Output Control
DESCRIPTION
Daisy Chaining Multiple devices –
multichannel off one PCM feed.
0 = No Output
1 = Output on pin 23.
The following diagram illustrates timing for a daisy chain with 2 WM8742 devices.
Figure 21 Audio Interface Daisy Chaining Timing
w
PD, Rev 4.3, February 2013
26
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