WM8956 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

WM8956

Hi-Fi DAC with 1W Stereo Class D Speaker Drivers and Headphone Drivers

Cirrus Logic 

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WM8956

Production Data

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised in

Table 27. MS selects audio interface operation in master or slave mode. In Master mode BCLK and

DACLRC are outputs. The frequency of DACLRC is set by the DACDIV bits and the frequency of

BCLK is set by the BCLKDIV bits (See "Clocking and Sample Rates"). In Slave mode BCLK and

DACLRC are inputs.

REGISTER

ADDRESS

R7 (07h)

Digital Audio

Interface

Format

BIT

LABEL

7

BCLKINV

6

MS

5

DLRSWAP

4

LRP

3:2 WL[1:0]

1:0 FORMAT[1:0]

Table 27 Audio Data Format Control

DEFAULT

DESCRIPTION

0

BCLK invert bit (for master and slave

modes)

0 = BCLK not inverted

1 = BCLK inverted

0

Master / Slave Mode Control

0 = Enable slave mode

1 = Enable master mode

0

Left/Right DAC Channel Swap

0 = Output left and right data as normal

1 = Swap left and right DAC data in

audio interface

0

Right, left and I2S modes – LRCLK

polarity

0 = normal LRCLK polarity

1 = invert LRCLK polarity

DSP Mode – mode A/B select

0 = MSB is available on 2nd BCLK rising

edge after LRC rising edge (mode A)

1 = MSB is available on 1st BCLK rising

edge after LRC rising edge (mode B)

10

Audio Data Word Length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits (see Note)

10

Audio Data Format Select

00 = Right justified

01 = Left justified

10 = I2S Format

11 = DSP Mode

Note: Right Justified mode does not support 32-bit data.

AUDIO INTERFACE OUTPUT TRISTATE

Register bit TRIS, register 24(18h) bit[3] can be used to switch DACLRC and BCLK to inputs. In Slave

mode (MS=0) DACLRC and BCLK are by default configured as inputs (see Table 28).

REGISTER BIT LABEL DEFAULT

ADDRESS

DESCRIPTION

R24 (18h)

Additional

Control (2)

3

TRIS

0

Switches DACLRC and BCLK to inputs.

0 = DACLRC and BCLK are inputs (slave mode)

or outputs (master mode)

1 = DACLRC and BCLK are inputs

Table 28 Tri-stating the Audio Interface

w

PD, November 2011, Rev 4.1

46

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