WM8956 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8956' PDF : 80 Pages View PDF
WM8956
Production Data
The class D switching clock should not be disabled when the speaker outputs are active, as
this would prevent the speaker outputs from functioning. The class D switching clock
frequency should not be altered while the speaker outputs are active as this may generate an
audible click.
Table 31 shows the clocking and sample rate controls for MCLK input, BCLK output (in master
mode), DACs, class D outputs and GPIO clock output. Refer to Table 32 for example clocking
configurations.
REGISTER
ADDRESS
R4 (04h)
Clocking (1)
BIT
LABEL
5:3 DACDIV
[2:0]
2:1 SYSCLKDIV
[1:0]
0
CLKSEL
R8 (08h)
Clocking (2)
8:6 DCLKDIV
3:0 BCLKDIV[3:0]
Table 31 DAC and BCLK Control
DEFAULT
DESCRIPTION
000
00
0
111
0000
DAC Sample rate divider (Also
determines DACLRC in master mode)
000 = SYSCLK / (1.0 * 256)
001 = SYSCLK / (1.5 * 256)
010 = SYSCLK / (2 * 256)
011 = SYSCLK / (3 * 256)
100 = SYSCLK / (4 * 256)
101 = SYSCLK / (5.5 * 256)
110 = SYSCLK / (6 * 256)
111 = Reserved
SYSCLK Pre-divider. Clock source
(MCLK or PLL output) will be divided by
this value to generate SYSCLK.
00 = Divide SYSCLK by 1
01 = Reserved
10 = Divide SYSCLK by 2
11 = Reserved
SYSCLK selection
0 = SYSCLK derived from MCLK
1 = SYSCLK derived from PLL output
Class D switching clock divider.
000 = Reserved
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 6
101 = SYSCLK / 8
110 = SYSCLK / 12
111 = SYSCLK / 16
BCLK Frequency (Master Mode)
0000 = SYSCLK
0001 = SYSCLK / 1.5
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4
0101 = SYSCLK / 5.5
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = SYSCLK / 11
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 22
1100 = SYSCLK / 24
1101 to 1111 = SYSCLK / 32
w
PD, November 2011, Rev 4.1
50
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