WM8956 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8956' PDF : 80 Pages View PDF
WM8956
Production Data
Setting the WL8 register bit allows the device to operate with 8-bit data. In this mode it is possible to
use 8 BCLK cycles per LRC frame. When using DSP mode B, this allows 8-bit data words to be
output consecutively every 8 BCLK cycles and can be used with 8-bit data words using the A-law and
u-law companding functions.
BIT7
SIGN
BIT[6:4]
EXPONENT
Table 30 8-bit Companded Word Composition
BIT[3:0]
MANTISSA
120
100
80
60
40
20
0
0
u-law Companding
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Normalised Input
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
Figure 32 µ-Law Companding
A-law Companding
120
100
80
60
40
20
0
0
0.2
0.4
0.6
0.8
Normalised Input
Figure 33 A-Law Companding
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
w
PD, November 2011, Rev 4.1
48
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