WM8960 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8960' PDF : 91 Pages View PDF
WM8960
Production Data
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised in
Table 33. MS selects audio interface operation in master or slave mode. In Master mode BCLK,
ADCLRC and DACLRC are outputs. The frequency of ADCLRC and DACLRC is set by the bits
ADCDIV and DACDIV and the frequency of BCLK is set by the bits BCLKDIV (See "Clocking and
Sample Rates"). In Slave mode BCLK, ADCLRC and DACLRC are inputs.
REGISTER
ADDRESS
R7 (07h)
Digital Audio
Interface
Format
BIT
LABEL
8
ALRSWAP
7
BCLKINV
6
MS
5
DLRSWAP
4
LRP
3:2 WL[1:0]
1:0 FORMAT[1:0]
Table 33 Audio Data Format Control
DEFAULT
DESCRIPTION
0
Left/Right ADC channel swap
1 = Swap left and right ADC data in
audio interface
0 = Output left and right data as normal
0
BCLK invert bit (for master and slave
modes)
0 = BCLK not inverted
1 = BCLK inverted
0
Master / Slave Mode Control
0 = Enable slave mode
1 = Enable master mode
0
Left/Right DAC Channel Swap
0 = Output left and right data as normal
1 = Swap left and right DAC data in
audio interface
0
Right, left and I2S modes – LRCLK
polarity
0 = normal LRCLK polarity
1 = invert LRCLK polarity
DSP Mode – mode A/B select
0 = MSB is available on 2nd BCLK rising
edge after LRC rising edge (mode A)
1 = MSB is available on 1st BCLK rising
edge after LRC rising edge (mode B)
10
Audio Data Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits (see Note)
10
Audio Data Format Select
00 = Right justified
01 = Left justified
10 = I2S Format
11 = DSP Mode
Note: Right Justified mode does not support 32-bit data.
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PD, August 2013, Rev 4.2
52
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