WM8960 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8960' PDF : 91 Pages View PDF
Production Data
WM8960
AUDIO INTERFACE OUTPUT TRISTATE
Register bit TRIS, register 24(18h) bit[3] can be used to tristate the ADCDAT pin and switch
ADCLRC, DACLRC and BCLK to inputs. In Slave mode (MS=0) ADCLRC, DACLRC and BCLK are
by default configured as inputs and only ADCDAT will be tri-stated, (see Table 34).
When the ADCLRC/GPIO1 pin is configured as a GPIO, this pin will not be tristated by the TRIS
register bit.
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
R24 (18h)
Additional
Control (2)
3
TRIS
0
Tristates ADCDAT and switches ADCLRC,
DACLRC and BCLK to inputs.
0 = ADCDAT is an output; ADCLRC, DACLRC
and BCLK are inputs (slave mode) or outputs
(master mode)
1 = ADCDAT is tristated; DACLRC and BCLK
are inputs; ADCLRC is an input (when not
configured as a GPIO)
Table 34 Tri-stating the Audio Interface
MASTER MODE ADCLRC AND DACLRC ENABLE
In master mode, by default ADCLRC clock generator is disabled and will output a logic 0 when the
ADCs are both disabled and DACLRC clock generator is disabled and will output a logic 0 when the
DACs are both disabled.
Register bit LRCM, register 24 (18h) bit[2] changes the control so that the ADCLRC and DACLRC
clock generators are both disabled only when both ADCs and both DACs are disabled. This enables
the user to use e.g. ADCLRC for both ADC and DAC LRCLK and disable the ADC when DAC only
operation is required, (see Table 35).
When ADCLRC is configured as a GPIO (using ALRCGPIO), DACLRC is used for the ADCs and the
DACs and will only be disabled in master mode when both ADCs and both DACs are disabled.
Figure 33 Master Mode Clock Output Control
w
PD, August 2013, Rev 4.2
53
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