WM8960 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8960' PDF : 91 Pages View PDF
WM8960
Production Data
REGISTER
ADDRESS
R8 (08h)
Clocking (2)
BIT
LABEL
8:6 DCLKDIV
3:0 BCLKDIV[3:0]
Table 39 ADC, DAC and BCLK Control
DEFAULT
DESCRIPTION
111
0000
Class D switching clock divider.
000 = SYSCLK / 1.5
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 6
101 = SYSCLK / 8
110 = SYSCLK / 12
111 = SYSCLK / 16
BCLK Frequency (Master Mode)
0000 = SYSCLK
0001 = SYSCLK / 1.5
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4
0101 = SYSCLK / 5.5
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = SYSCLK / 11
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 22
1100 = SYSCLK / 24
1101 to 1111 = SYSCLK / 32
SYSCLK
(=MCLK OR PLL OUTPUT)
ADCDIV OR
DACDIV
(MHz)
000 (=1)
001 (=1.5)
010 (=2)
12.288
011 (=3)
100 (=4)
101 (=5.5)
110 (=6)
111
000 (=1)
001 (=1.5)
010 (=2)
11.2896
011 (=3)
100 (=4)
101 (=5.5)
110 (=6)
111
000 (=1)
001 (=1.5)
010 (=2)
2.048
011 (=3)
100 (=4)
101 (=5.5)
110 (=6)
111
Table 40 ADC and DAC Sample Rates
ADC / DAC SAMPLE
RATE (kHz)
48
32
24
16
12
(Not used)
8
Reserved
44.1
(Not used)
22.05
(Not used)
11.025
8.018
(Not used)
Reserved
8
(Not used)
(Not used)
(Not used)
(Not used)
(Not used)
(Not used)
Reserved
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PD, August 2013, Rev 4.2
58
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