WM8960 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8960' PDF : 91 Pages View PDF
Production Data
WM8960
Although the ADC and DAC can run at different sample rates, they share the same bit clock pin
BCLK.
When operating in master mode, register bits BCLKDIV[3:0] should be set to an appropriate value to
ensure that there are sufficient BCLK cycles to transfer the complete data word from the ADCs and to
the DACs.
When operating in slave mode, the host device must provide sufficient BCLK cycles to transfer
complete data words to the ADCs and DACs.
Table 41 shows the maximum word lengths supported for a given SYSCLK and BCLKDIV, assuming
that either the ADCs or DACs are running at maximum rate (i.e. ADCDIV[2:0]=000 or
DACDIV[2:0]=000).
SYSCLK
BCLKDIV[3:0]
(=MCLK OR PLL OUTPUT)
(MHz)
0000 (=1)
0001 (=1.5)
0010 (=2)
0011 (=3)
0100 (=4)
0101 (=5.5)
0110 (=6)
12.288
0111 (=8)
1000 (=11)
1001 (=12)
1010 (=16)
1011 (=22)
1100 (=24)
1101 (=32)
1110 (=32)
1111 (=32)
0000 (=1)
0001 (=1.5)
0010 (=2)
0011 (=3)
0100 (=4)
0101 (=5.5)
0110 (=6)
11.2896
0111 (=8)
1000 (=11)
1001 (=12)
1010 (=16)
1011 (=22)
1100 (=24)
1101 (=32)
1110 (=32)
1111 (=32)
Table 41 BCLK Divider in Master Mode
BCLK RATE MAXIMUM WORD LENGTH
(MASTER MODE) (AT MAXIMUM ADC OR
(MHz)
DAC SAMPLE RATE)
12.288
32
8.192
32
6.144
32
4.096
32
3.072
32
2.2341818
20
2.048
20
1.536
16
1.117091
8
1.024
8
0.768
8
0.558545
N/A
0.512
N/A
0.384
N/A
0.384
N/A
0.384
N/A
11.2896
32
7.5264
32
5.6448
32
3.7632
32
2.8224
32
2.052655
20
1.8816
20
1.4112
16
1.026327
8
0.9408
8
0.7056
8
0.513164
N/A
0.4704
N/A
0.3528
N/A
0.3528
N/A
0.3528
N/A
OTHER SAMPLE RATE CONTROL BITS
The ALC, de-emphasis filter and 3D stereo enhance functions all need to be configured for the
chosen sample rate when in use, as show in Table 42.
ADC_ALC_SR should be configured to match the chosen ADC sample rate.
w
PD, August 2013, Rev 4.2
59
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