XR16C872IQ View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C872IQ' PDF : 60 Pages View PDF
Preliminary
XR16C872
An example to program the FIFO trigger level:
write LCR with 0xBF
; point to enhanced registers
set FCTR bit4-5 to logic 1 ; select trigger Table-D
set FCTR bit-7 to logic 0 ; program RX FIFO trigger level
write TRG with 0x60
; set your RX trigger level to 96
set FCTR bit-7 to logic 1 ; program TX FIFO trigger level
write TRG with 0x08
; set your TX trigger level to 8
write LCR with 0x03
; set operating parameters
Receive data ready interrupt will activates when RX
FIFO fills up to 96 data bytes while the transmit empty
interrupt gets set when data is empty to 8 bytes.
Interrupt Status Register (ISR)
The UART provides six levels of prioritized interrupts
to minimize external software interaction. The Interrupt
Status Register (ISR) provides the user with six inter-
rupt status bits. Performing a read cycle on the ISR will
provide the user with the highest pending interrupt level
to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the
interrupt status register is read, the interrupt status is
cleared. However it should be noted that only the
current pending interrupt is cleared by the read. A lower
level interrupt may be seen after re-reading the inter-
rupt status bits. The Interrupt Source Table 6 (below)
shows the data values (bit 0-5) for the six prioritized
interrupt levels, the interrupt sources associated with
each of these interrupt levels, and how to clear each
interrupt (INT).
Priority
[ ISR BITS ]
Level Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Source of the Interrupt
1
0 0 0 1 1 0 LSR (Receiver Line Status Register)
2
0 0 0 1 0 0 RXRDY (Received Data Ready)
2
0 0 1 1 0 0 RXRDY (Receive Data time out)
3
0 0 0 0 1 0 TXRDY ( Transmitter Holding Register Empty)
4
0 0 0 0 0 0 MSR (Modem Status Register)
5
0 1 0 0 0 0 RXRDY (Rcv. Xoff signal / Special character)
6
1 0 0 0 0 0 CTS, RTS change of state
Table 4. Interrupt Priority and Source
INT Clears
After A
LSR read
LSR read
LSR read
ISR read
MSR read
ISR read
MSR read
Rev. P1.00
31
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