XR16C872IQ View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C872IQ' PDF : 60 Pages View PDF
XR16C872
Preliminary
ISR BIT-0:
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (normal default condi-
tion)
ISR BIT 1-3: (logic 0 or cleared is the default condition)
These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2, and 3 (See Interrupt Source
Table).
ISR BIT 4-5: (logic 0 or cleared is the default condition)
These bits are enabled when EFR bit-4 is set to a logic
1. ISR bit-4 indicates that matching Xoff character(s)
have been received. ISR bit-5 indicates that CTS# or
RTS# condition have changed. Note that once set to a
logic 1, the ISR bit-4 will stay a logic 1 until Xon
character(s) is received or upon a read to register ISR.
BIT-1
0
0
1
1
BIT-0
0
1
0
1
Word Length
5
6
7
8
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in
conjunction with the programmed word length.
BIT-2
0
1
1
Word
5,6,7,8
5
6,7,8
Stop Bit
Length
(Bit Time(s))
1
1-1/2
2
ISR BIT 6-7: (logic 0 or cleared is the default condition)
These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFOs
are enabled.
Line Control Register (LCR)
LCR BIT-3:
Parity or no parity can be selected via this bit.
Logic 0 = No parity (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, the receiver checks and reports parity error in the
LSR register. The parity is not presented in the
received data byte.
The Line Control Register is used to specify the
asynchronous data communication format. The word
length, the number of stop bits, and the parity are
selected by writing the appropriate bits in this register.
This register also has a secondary function to select
two other register sets. The first is by setting bit-7 = 1
to select the baud rate divisor (DLL and DLM) registers,
and the second set of registers is selected when a “BF”
hex is written to LCR to select the enhanced register
set.
LCR BIT 0-1: (logic 0 or cleared is the default condi-
tion).
These two bits specify the word length to be transmit-
ted or received. The upper unused bit(s) in the received
data byte is set to zero.
Rev. P1.00
LCR BIT-4:
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1’s in the transmitted data. The
receiver must be programmed to check the same
format. (normal default condition)
Logic 1 = EVEN Parity is generated by forcing an even
number of logic 1’s in the transmitted data. The
receiver must be programmed to check the same
format.
LCR BIT-5:
If the parity bit is enabled, LCR BIT-5 selects the forced
parity format.
LCR BIT-5 = logic 0, parity is not forced (normal default
condition)
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit
is forced to a logical 1 for the transmit and receive data.
32
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