XR16C872IQ View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C872IQ' PDF : 60 Pages View PDF
XR16C872
Preliminary
TRIGGER LEVEL/FIFO COUNT REGISTER (TRG)
This register is only accessible when LCR is set to
0xBF.
This register provides the user programmable transmit
or receive trigger level from byte 0 to 128 (0xFF), and
reading the number of data bytes in the transmit or
receive FIFO.
TRG BIT 0-7: Write only.
This register sets the user programmable transmit or
receive FIFO trigger levels. FCTR bit-7 must be set
and point to the transmitter or receiver prior to
programming the trigger level.
TRG BIT 0-7: Read only.
Transmit / receive FIFO count. Number of characters
in transmit or receive FIFO can be read via this
register. FCTR bit-7 must be set and point to the
transmitter or receiver prior to reading the FIFO count.
ENHANCED MODE SELECT REGISTER (EMSR)
EMSR BIT-1: Write only
0 = Normal.
1 = Alternate receive - transmit FIFO count. When
EMSR Bit-0=1 and EMSR Bit-1=1, Scratch Pad Reg-
ister is used to provide the receive - transmit FIFO
count when it is read every alternate read cycle. The
TRG Bit-7 will provide FIFO count mode information,
TRG Bit-7=0 receive mode, TRG Bit-7=1 transmit
mode.
EMSR BIT-2: Write only
This bit is not available in the 872.
EMSR BIT4 and 5 - Write only
These bits select the RTS flow control hysteresis and
are associated with FCTR bit 0 and 1. The RTS
hysteresis is reference to the RX FIFO trigger level.
Below table shows the 16 selectable hysteresis.
EMSR EMSR FCTR FCTR RTS Hysteresis
Bit-5 Bit-4 Bit-1 Bit-0 (characters)
This register is only accessible when LCR is set to
0xBF and FCTR Bit-6 is set to logic 1.
EMSR BIT-0: Write only
0 = Receive FIFO count register. The Scratch Pad
Register (SPR) is used to provide the receive FIFO
count when it is read.
1 = Transmit FIFO count register. The Scratch Pad
Register (SPR) is used to provide the transmit FIFO
count when it is read.
Example to read the number of character count in TX
or RX FIFO.
0
0
0
0 Next level
0
0
0
1 +/- 4
0
0
1
0 +/- 6
0
0
1
1 +/- 8
0
1
0
0 +/- 8
0
1
0
1 +/- 16
0
1
1
0 +/- 24
0
1
1
1 +/- 32
1
0
0
0 +/- 12
1
0
0
1 +/- 20
In the Initialization routine:
set LCR to 0xBF
; point to enhanced registers
1
0
1
0 +/- 28
1
0
1
1 +/- 36
set FCTR bit-6 to logic 1
; swap SPR to be FIFO counters and
; point to EMSR register
set LCR to operating parameters
- in RX routine -
set EMSR bit-0 to logic 0
; set to read RX FIFO count
1
1
0
0 +/- 40
1
1
0
1 +/- 44
1
1
1
0 +/- 48
1
1
1
1 +/- 52
read SPR
; obtain RX FIFO count
or
- in TX routine -
set EMSR bit-0 to logic 1
; read TX FIFO count
EMSR BIT 6-7:
Reserved for future use.
read SPR
; obtain TX FIFO Count
Rev. P1.00
38
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