XR16C872IQ View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C872IQ' PDF : 60 Pages View PDF
Preliminary
XR16C872
is unloaded to the lower limit of the hysteresis. The
state of this register bit changes with the status of the
hardware flow control. RTS# functions normally when
hardware flow control is disabled.
0 = Automatic RTS flow control is disabled. (normal
default condition)
1 = Enable Automatic RTS flow control.
EFR bit-7:
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled.
(normal default condition)
Logic 1 = Enable Automatic CTS flow control. Trans-
mission stops when CTS# goes to a logical 1. Trans-
mission resumes when the CTS# pin returns to a
logical 0.
FEATURE CONTROL REGISTER (FCR)
This register is only accessible when LCR is set to
0xBF.
FCTR BIT 0-1:
User selectable RTS# delay or hysteresis for hardware
flow control application. After reset, these bits are set
to logic 0 to select the next trigger level on the RX FIFO
trigger level (FCR bit 6-7,Table-A). These bits are also
associated with EMSR bit-4 and 5 for the hysteresis
control. See EMSR register for more details.
FCTR BIT-2:
0 = Select RX input as encoded IrDa data.
1 = Select RX input as active high encoded IrDa data.
FCTR BIT-3:
Auto RS485 Half Duplex Direction control.
*OP1# output is not available in the 872, however, it
does change the behavior of the transmit empty inter-
rupt.
0 = Transmitter generates an interrupt when transmit
holding register becomes empty while transmit shift
register is still shifting data out.
1 = Enable Auto RS485 Half Duplex Direction Control.
The transmit empty interrupt generation is delayed
until the Transmitter Shift Register (TSR) becomes
empty.
FCTR BIT 4-5:
Transmit / receive trigger table select.
FCTR
Bit-5
0
0
1
1
FCTR
Bit-4
0
1
0
1
Trigger
Table
Table-A (TX/RX)
Table-B (TX/RX)
Table-C (TX/RX)
Table-D (TX/RX)
FCTR BIT-6:
Scratch Pad Register (SPR) or EMSR select.
0 = Scratch Pad Register (SPR) is selected as general
read and write register. 16C550 compatible mode.
1 = FIFO count register, Enhanced Mode Select
Register (EMSR). Number of characters in transmit or
receive holding register can be read via Scratch Pad
Register when this bit is set. Enhanced Mode is
selected when it is written into it.
FCTR BIT-7:
Programmable trigger register select.
0 = Receiver programmable trigger level register (TRG)
is selected.
1 = Transmitter programmable trigger level register
(TRG) is selected.
Rev. P1.00
37
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