XR16C872IQ View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C872IQ' PDF : 60 Pages View PDF
Preliminary
XR16C872
ECR Bit 5-7:
This field can be set to any value if the current value
is 000 or 001. If the current value is not 000 or 001, then
the field can only be written to 000 or 001. The modes
are defined as:
Mode
000
001
010
011
100
101
110
111
Name
SPP
PS2
PPF
ECP
EPP
-
TST
CFG
Description
Standard, output only. DCR bit-5
is forced to “0”.
Bi-directional PS/2 parallel port.
FIFO is disabled
FIFOed, output only. DCR bit-5
is forced to “0”.
ECP FIFOed port with RLE de-
compression. FIFO direction is
controlled by DCR Bit-5.
EPP mode.
reserved
FIFO test mode. FIFO is acces-
sible via TFIFO register.
Configuration A/B register en-
able.
OPERATION
SPP MODE
This is ECR mode 000 (system RESET mode).
In this output-only mode the host data is registered to
PD[7:0] at the trailing edge of IOW#; PDIR is driven
low; STROBE#, AUTOFD#, INIT#, and SELCTIN# are
open-drain; and all timing is managed by the host
through DSR and DCR registers.
PS2 MODE
This is ECR mode 001.
In this bi-directional mode the host output data is
registered to PD[7:0] at the trailing edge of IOW#, PDIR
is driven by DIR to allow peripheral data input,
AUTOFD#, INIT#, and SELCTIN# are totem-pole, and
all timing is managed by the host through DSR and
DCR registers.
PPF MODE
This is ECR mode 010.
In this output-only mode the host data is written to the
FIFO with I/O writes to address 400 or by DMA writes;
PDIR is driven low. FIFO data is automatically regis-
tered to PD[7:0] whenever the FIFO-E bit is low (data
available), and timing is generated by controller logic
that handshakes STROBE# (controller) with BUSY
(peripheral).
ECP MODE
This is ECR mode 011.
In this bi-directional mode the host data is written to the
FIFO with I/O writes to address 000, 400 or DMA; PDIR
is driven by DIR (can only be set in ECR mode 001);
AUTOFD#, INIT, and SELCTIN# are totem-pole. I/O
writes to address 000 will write a low into the FIFO tag
bit, while I/O writes to address 400 or DMA will insert
a high.
ECP FORWARD MODE (PDIR = 0)
FIFO data is automatically registered to PD[7:0] when-
ever the FIFO-E bit is low (data available), and timing
is generated by controller logic that handshakes
STROBE# (controller) with BUSY (peripheral). Data
from the FIFO tag bit is output on AUTOFD# after being
registered simultaneous with FIFO data.
ECP REVERSE MODE (PDIR = 1)
PD[7:0] data and BUSY are latched into the FIFO and
tag bit respectively at the trailing edge of AUTOFD# if
FIFO-F = 0. Timing is generated by controller logic that
handshakes ACK# (peripheral) with AUTOFD# (con-
troller).
EPP MODE
This is ECR mode 100.
In this bi-directional mode, I/O writes will latch host
output data at the trailing edge of IOW#, and peripheral
input data will be latched at the trailing edge of
SELCTIN# or AUTOFD#. PDIR, and STROBE# are
driven by the state of IOW# (DCR bits 5 and 0 must be
set low).
Rev. P1.00
43
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