XR16C872IQ View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C872IQ' PDF : 60 Pages View PDF
Preliminary
XR16C872
Nibble Mode Data Transfer Cycle
1. Host signals ability to take data by asserting HostBusy low.
2. Peripheral responds by placing first nibble on status lines.
3. Peripheral signals valid nibble by asserting PtrClk low.
4. Host sets HostBusy high to indicate that it has received the nibble and is not ready for another nibble.
5. Peripheral sets PtrClk high to acknowledge host.
Signal
Name
STROBE#
AUTOFD#
Signal
Type
O
O
EPP mode
Name
Write#
DataStb#
SELCTIN#
O
AddrStb#
INIT#
ACK#
BUSY
O
Reset#
I
Intr#
I
Wait#
PE
SELECT
ERR#
PD0-PD7
I
User defined
I
User defined
I
User defined
O
AD0-AD7
Description
Active low. Indicates a write operation, high for a read cycle.
Active low. Indicates a Data-Read or Data-Write operation is in
process.
Active low. Indicates an Address-Read or Address-Write
operation is in process.
Active low. Peripheral reset.
Peripheral interrupt. Used to generate an interrupt to the host.
Handshake signal. When low it indicates that is okay to start a cycle,
when high it indicates that it is okay to end the cycle.
Not used.
Not used.
Not used.
Bi-directional address / data lines.
Table 10. EPP Mode Signal Description
EPP Mode Data Transfer Cycle
1. Program executes an I/O write cycle to EPP Data Port-4.
2. The Write# line is asserted and the data is output to the parallel port.
3. The DataStb# is asserted, since Write# is asserted low.
4. The port waits for the acknowledge from the peripheral, Write# deasserted.
5. The DataStr# is deasserted and EPP cycle ends.
6. Write# is asserted low to indicate that the next cycle may begin.
Rev. P1.00
47
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