XR16C872IQ View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR16C872IQ' PDF : 60 Pages View PDF
XR16C872
Preliminary
EPP mode allows buffered access between the PC bus
and the peripheral with timing provided by the periph-
eral via BUSY handshake into IOCHRDY. I/O cycles
with address 003 - 007 will immediately drive
IOCHRDY low. STROBE# will go low and PD[7:0] is
allowed to change (write cycles) after BUSY has been
low for at least 60n second. (This delay may have
elapsed prior to cycle initiation). It is immediately
followed by a low driven on SELCTIN# for address 003
or AUTOLF# (DATASTB*) for address 004 - 007 (read
and write cycles). When BUSY returns high for a
minimum of 60n second, IOCHRDY and the active
strobe will be driven high -allowing the host to complete
the I/O transaction.
To prevent a system stall, a 10 msecond TimeOut
aborts the cycle if it expires before BUSY returns high.
This TimeOut also sets bit 0 of DCR, which is cleared
by disabling EPP mode or writing a high to DCR bit 0.
TST MODE
This is ECR mode 110.
This mode allows data to be transferred (read or write
in any direction) between the FIFO and host at address
400 or DMA without activating the control interface (no
data is transferred to/from the peripheral). PDIR is
driven by DIR (can only be set in ECR mode 001).
Performing I/O cycles in this mode allows software to
test for the value of FIFOThreshold (FT) for both output
and input directions.
CFG MODE
This is ECR mode 111.
This mode enables I/O access to the configuration
registers CONF-A and CONF-B and disables I/O ac-
cess to the FIFO.
IRQ
The module has four sources of interrupt which may be
directed to IRQ5, IRQ7, IRQ9 (see CONF-B). In PnP
mode IRQ assignment is made through auto configu-
ration.
1) When DCR bit 4 (AIE) is high and ACK# is low the
interrupt is active.
2) When ECP mode is active, if ECR bit 4 is low when
ERROR transitions low or ECR bit 4 transitions low
when Fault# is low an interrupt pulse of at least 200n
seconds will be generated.
3) In FIFO modes (PPF, ECP, or TST) with ECR bit 3
(DMA) low, an interrupt pulse of at least 200n
seconds will be generated when ECR bit 2 (SI) is set
low if there are at least 8 empty bytes in the FIFO
and PDIR = 0 or there are at least 8 filled bytes in
the FIFO and PDIR = 1. This interrupt will automati-
cally disable itself by setting ECR bit 2 high.
4) In FIFO modes (PPF, ECP, or TST) with (DMA
request enabled), an interrupt pulse of at least 200n
seconds will be generated when TC is received if
PD-ACK is low. This interrupt will automatically
disable itself and the DMA request by setting ECR
bit 2 high.
DMA
DMA cycles occur only between the host and the FIFO
data port (address 400) for PPF, ECP, or TST modes.
DRQ(1, 2, or 3) is selected through auto configuration
in PnP mode and they will be driven high if ECR bit 3
(DMA) is high and ECR bit 2 (SI) is low when {PDIR =
0 and FIFO-F = 0} or {PDIR = 1 and FIFO-E = 0} or TST
mode is active. Manual mode defaults to DRQ3.
When the selected DACKn#(1, 2, or 3) is low, IOW# will
transfer host data to the FIFO and IOR# will transfer
FIFO data to the host. The selected DREQn will be
driven low to terminate the DMA channel when {PDIR
= 0 and FIFO-F = 1} or {PDIR = 1 and FIFO-E = 1} or
ECR bit 2 (SI) goes high (interrupt condition 4 above)
or more than 32 consecutive DMA data cycles (read or
write) have occurred.
FIFO-F and FIFO-E terminated cycles will automati-
cally restart when their state returns low. Consecutive
cycle termination will automatically restart because
the counter is reset when the selected DACKn# goes
high. TC terminated cycles can only be restarted by
the host setting ECR bit 2 (SI) low again.
Rev. P1.00
44
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