XRT7302 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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REV. 1.1.0
SYSTEM DESCRIPTION
A functional block diagram of the XRT7302 E3/DS3/
STS-1 Transceiver IC is presented in Figure 6. In
general, the XRT7302 device contains three distinct
sections:
• The Transmit Section - Channels 1 and 2
• The Receive Section - Channels 1 and 2
• The Microprocessor Serial Interface
Each of these sections are briefly discussed below.
THE TRANSMIT SECTION (CHANNELS 1 AND 2)
The Transmit Section, within each Channel, accepts
TTL/CMOS level signals from the "Terminal Equip-
ment" in either a "Single-Rail" or "Dual Rail" format.
The Transmit Section will then take this data and do
the following.
• Encode this data into the B3ZS format (if the DS3
or SONET STS-1 Modes have been selected) or
into the HDB3 format (if the E3 Mode has been
selected).
• Convert the CMOS level B3ZS or HDB3 encoded
data into pulses with shapes that are compliant with
the various industry standard pulse template
requirements.
• Drive these pulses onto the line via the TTIP and
TRing output pins, across a 1:1 Transformer.
NOTE: Note: The Transmit Section will drive a "1" (or a
"Mark") onto the line by driving either a positive or negative
polarity pulse across the 1:1 Transformer, within a given bit
period. The Transmit Section will drive a "0" (or a "Space")
onto the line by driving no pulse onto the line.
THE RECEIVE SECTION (CHANNELS 1 AND 2)
The Receive Section, within each Channel, receives
a bipolar signal from the line, through the RTIP and
RRing pins via a "1:1 Transformer" or via a "0.01µF
Capacitor". The Receive Section will do the following.
• Adjust the signal level through an AGC circuit.
• Optionally equalize this signal for cable loss.
• The "sliced" data will be routed to the "HDB3/B3ZS"
Decoder; during which the data content (as trans-
mitted by the Remote Terminal Equipment) is
restored to its original content.
• The recovered clock and data will be output to the
"Local Terminal Equipment", in the form of CMOS
level signals, via the RPOS, RNEG, RxClk1 and
RxClk2 output pins.
THE MICROPROCESSOR SERIAL INTERFACE
The XRT7302 device can be configured to operate in
either the "Hardware" Mode or the "Host" Mode.
Each of these modes will be discussed below.
THE HARDWARE MODE
When the XRT7302 device is operating in the "Hard-
ware Mode", then the following is true.
1. The Microprocessor Serial Interface block is
disabled.
2. The XRT7302 device is configured via input pin
settings.
The XRT7302 device can be configured to operate in
the "Hardware Mode" by tying the "Host/HW" input
pin (pin 8) to GND.
Each of the pins associated with the Microprocessor
Serial Interface will take on their alternative role, as
defined in Table 1.
TABLE 1: ROLE OF MICROPROCESSOR SERIAL INTERFACE
PINS WHEN THE XRT7302 DEVICE IS OPERATING IN THE
"HARDWARE" MODE
PIN #
17
18
19
20
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PIN NAME
CS/(ENDECDIS)
SClk/(RxOFF2)
SDI/(RxOFF1)
SDO/(E3_CH1)
REGR/(RClkINV)
FUNCTION, WHILE IN HARDWARE
MODE
ENDECDIS
RxOFF2
RxOFF1
E3_CH1
RCKLKINV
Additionally, when the XRT7302 device is operating in
the "Hardware" Mode, all of the remaining input pins
become active.
THE HOST MODE
The XRT7302 device can be configured to operate in
the "Host" Mode by tying the "Host/HW" input pin (pin
8) to VDD.
When the XRT7302 device is operating in the "Host
Mode", then the following is true.
1. The Microprocessor Serial Interface block is
enabled. Writing the appropriate data into the
on-chip Command Registers makes many config-
uration selections.
2. All of the following input pins are disabled.
• Pin 1 - TxLEV1
• Pin 2 - TAOS1
• Pin 21 - STS-1/DS3_Ch1
• Pin 24 - LLB1
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