XRT7302IQ80 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT7302IQ80' PDF : 77 Pages View PDF
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.0
If the user wishes to transmit data from the "Terminal
Equipment" to the Transmit Section within a given
channel in a "single-rail" format (e.g., a binary data
stream), without having to convert it into a "dual-rail"
format; the user can do the following.
a. Configure the XRT7302 device to operate in the
"Host" Mode.
b. Access the Microprocessor Serial Interface, and
execute the following steps, for each Channel.
To Configure Channel 1 to accept Single-Rail Data
from the Terminal Equipment:
Write a "1" into the "TxBIN1" (TRANSMIT BINary) bit-
field, within Command Register 1 (for Channel 1), as
depicted below.
COMMAND REGISTER 1 (ADDRESS = 0X01)
D4
D3
TxOFF1 TAOS1
x
x
D2
TxClkINV1
x
D1
D0
TxLEV1 TxBIN1
x
1
NOTE: Executing this write operating to Command Register
1 will not configure the Transmit Section (within Channel 2)
to accept "Single-Rail" data from the Terminal Equipment.
To Configure Channel 2 to accept Single-Rail Data
from the Terminal Equipment:
Write a "1" into the "TxBIN2" bit-field, within Com-
mand Register 9 (for Channel 2), as depicted below.
COMMAND REGISTER 9 (ADDRESS = 0X09)
D4
D3
D2
D1
D0
TxOFF2
x
TAOS2
x
TxClkINV2
x
TxLEV2 TxBIN2
x
1
NOTE: Executing this write operating to Command Register
CR9 will not configure the Transmit Section (within Channel
2) to accept Single-Rail data from the Terminal Equipment.
The Transmit Section (of each channel) will sample
this input pin on the "falling" edge of the TxClk clock
signal, and will encode this data into the appropriate
bipolar line signal across the TTIP and TRing output
pins.
NOTES:
1. In this mode, the Transmit Logic Block will ignore
the TNData input pin.
2. If the user configures the Transmit Section (within a
given channel) to accept "Single-Rail" data from the
Terminal Equipment, then the user must enable the
"B3ZS/HDB3" Encoder.
Figure 9 Illustrates the behavior of the TPData and
TxClk signals, when the Transmit Logic Block has
been configured to accept "single-rail" data from the
Terminal Equipment
FIGURE 9. ILLUSTRATION OF THE BEHAVIOR OF THE TPDATA AND TXCLK INPUT SGNALS, WHILE THE TRANSMIT
LOGIC BLOCK IS ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT
Data
1
1
0
TPData
TxClk
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIR-
CUITRY
The on-chip "Pulse-Shaping" circuitry (within the
Transmit Section of each Channel in the XRT7302
device) generates pulses of the appropriate shapes
and width, in order to meet the applicable pulse tem-
plate requirement. The widths of these "output" puls-
es are defined by the width of the "half-period" pulses
within the TxClk signal.
However, if the widths of the pulses, within the TxClk
clock signal are allowed to vary significantly, this
could jeopardize the chip's ability to generate Trans-
mit Output pulses of the appropriate width, and there-
by failing the applicable "Pulse Template" requirement
specification. As consequence, the chip's ability to
generate compliant pulses could depend upon the
duty cycle of the clock signal, applied to the TxClk in-
put pin.
The Transmit Clock Duty Cycle Adjust Circuitry ac-
cepts clock pulses from the TxClk input pin with duty
cycles ranging from 30% to 70%, and to regenerate
these signals at a 50% duty cycle.
31
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