XRT79L71_10 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT79L71_10' PDF : 609 Pages View PDF
REV. P2.0.0
PIN NAME
PTYPE[2:0]
PRELIMINARY
XRT79L71
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
Table 3: List and Brief Description of the Microprocessor Interface Pins
PIN/BALL
NUMBER
TYPE
DESCRIPTION
J14J15J1
I
Microprocessor Type Select input:
6
These three input pins permit the user to configure the Microprocessor Interface
block to readily support a wide variety of Microprocessor Interfaces. The rela-
tionship between the settings of these input pins and the corresponding Micro-
processor Interface configuration is presented below
PTYPE[2:0]
000
001
010
011
100
101
Microprcessor Interface mode
Intel-Asynchronous Mode
Motorola-Asynchronous Mode - (Motorola 68K)
Intel X86
Intel i960
IDT3051/52 (MIPS)
Power PC 403 Mode
DBEN
BLAST
J13
I Bi-directional Data Bus Enable Input pin:
This input pin permits the user to either enable or tri-state the Bi-Directional Data
Bus pins (D[7:0]).
Setting this input pin "low" enables the Bi-directional Data bus.
Setting this input "high" tri-states the Bi-directional Data Bus.
B15
I Last Burst Transfer Indicator input pin:
If the Microprocessor Interface is operating in the Intel-I960 Mode, then this
input pin is used to indicate (to the Microprocessor Interface block) that the cur-
rent data transfer is the last data transfer within the current burst operation.The
Microprocessor should assert this input pin (by toggling it "Low") in order to
denote that the current READ or WRITE operation (within a BURST operation)
is the last operation of this BURST operation.
NOTE: If the Microprocessor Interface has been configured to operate in the
Intel-Asynchronous, the Motorola-Asynchronous or the Power PC 403
Mode, then tie this input pin to GND.
2.1 Operating the Microprocessor Interface in the Intel-Asynchronous Mode
If the Microprocessor Interface has been configured to operate in the Intel-Asynchronous Mode, then the
following Microprocessor Interface pins will assume the role that is described below in Table 1b.
30
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