XRT79L71_10 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT79L71_10' PDF : 609 Pages View PDF
PRELIMINARY
XRT79L71
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
TABLE 4: THE ROLES OF VARIOUS MICROPROCESSOR INTERFACE PINS, WHEN CONFIGURED TO OPERATE IN THE
INTEL-ASYNCHRONOUS MODE
PIN NAME
PIN/BALL
NUMBER
TYPE
DESCRIPTION
DBEN
J13
I Data Bus Enable Input:
For Intel-Asynchronous Mode operation, either tie this pin to a logic "low"
or assert this pin (e.g., toggle it to a logic "low") anytime a READ opera-
tion is being performed with the Microprocessor Interface of the
XRT79L71.
BLAST
B15
I NONE - Tie this pin to GND
Configuring the Microprocessor Interface to operate in the Intel-Asynchronous Mode
Configure the Microprocessor Interface to operate in the Intel-Asynchronous Mode by tying the PTYPE[2:0]
pins/balls (e.g., Ball Numbers J14, J15 and J16, respectively) to GND.
Finally, if the Microprocessor Interface has been configured to operate in the Intel-Asynchronous Mode, then it
will perform READ and WRITE operations as described below.
2.1.1 The Intel-Asynchronous Read-Cycle
If the Microprocessor Interface (of the XRT79L71) has been configured to operate in the Intel-Asynchronous
Mode, then the Microprocessor should do all of the following, anytime it wishes to read out the contents of a
register or some location within the Receive LAPD Message buffer, the Receive Cell Extraction Memory or the
Transmit Cell Extraction Memory, (within the XRT79L71).
1. Place the address of the "target" register or buffer location (within the XRT79L71) on the Address Bus
input pins A[14:0].
2. While the µC/µP is placing this address value on the Address Bus, the Address Decoding circuitry (within
the user's system) should assert the CS (Chip Select) pin of the XRT79L71, by toggling it "low". This
action enables further communication between the µC/µP and the XRT79L71 Microprocessor Interface
block.
3. Toggle the ALE/AS (Address Latch Enable) input pin "high". This step enables the "Address Bus" input
drivers, within the Microprocessor Interface block of the XRT79L71.
4. After allowing the data on the Address Bus pins to settle (by waiting the appropriate "Address" Data
Setup time"), the µC/µP should toggle the ALE/AS pin "low". This step causes the XRT79L71 to "latch"
the contents of the "Address Bus" into its internal circuitry. At this point, the address of the register or
buffer locations (within the XRT79L71) has now been selected.
5. Next, the µC/µP should indicate that this current bus cycle is a "Read" Operation by toggling the RD/DS
(Read Strobe) input pin "low". This action also enables the bi-directional data bus output drivers of the
XRT79L71. At this point, the "bi-directional" data bus output drivers will proceed to drive the contents of
the "latched addressed" register (or buffer/memory location) onto the bi-directional data bus, D[7:0].
6. Immediately after the µC/µP toggles the "Read Strobe" (RD/DS) signal "low", the XRT79L71 will continue
to drive the RDY/DTACK output pin "high". The XRT79L71 does this in order to inform the µC/µP that the
data (to be read from the data bus) is "NOT READY" to be "latched" into the µC/µP. In this case, the µC/
µP should continue to hold the "Read Strobe" (RD/DS) signal "low" until it detects the RDY/DTACK output
pin toggling low.
7. After some settling time, the data on the "bi-directional" data bus will stabilize and can be read by the µC/
µP. At this time, the XRT79L71 will indicate that this data can be read by toggling the RDY/DTACK
(READY) signal "low".
8. After the µC/µP detects the RDY/DTACK signal (from the XRT79L71) toggling "low", it can then terminate
the Read Cycle by toggling the RD/DS (Read Strobe) input pin "high".
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